Senior Digital Design Engineer - Low-Power Mixed-Signal

Renesas

Arizona

Hybrid

USD 110,000 - 170,000

Full time

14 days+
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Benefits offered by this job

Remote work option
Employee Resource Groups

Job summary

Renesas Electronics in Chandler, AZ is seeking a Senior Digital Engineer to translate high level requirements into low-power digital circuits for mixed-signal data conversion and power management products. You will collaborate across silicon development stages from concept to mass production and work with analog and verification teams to deliver high-quality silicon solutions.

The role demands strong Verilog/SystemVerilog RTL skills, ASIC design experience, and a proactive approach to design

Qualifications

  • BS in Electrical/Electronics/Computer Engineering or related field.
  • Proficient in Verilog/SystemVerilog for digital CMOS design.
  • Experience in ASIC design flow and timing closure.

Responsibilities

  • Translate requirements into digital RTL design that meets timing, area, and power goals.
  • Collaborate with Analog and Verification teams to deliver silicon solutions.
  • Develop and review design documents and collateral.
  • Contribute to DFT strategy and testbench development.
  • Perform block- and top-level simulations and timing analysis.

Skills

Digital CMOS design
Verilog SystemVerilog
ASIC design methodology
Lint CDC RDC
UVM verification
Power management / low-power
English communication
Travel flexibility

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence simulators
ModelSim
UVM
Timing analysis tools

Job description

Renesas Electronics in Chandler, AZ is seeking a Senior Digital Engineer to translate high level requirements into low-power digital circuits for mixed-signal data conversion and power management products. You will collaborate across silicon development stages from concept to mass production and work with analog and verification teams to deliver high-quality silicon solutions.

The role demands strong Verilog/SystemVerilog RTL skills, ASIC design experience, and a proactive approach to design

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