Senior Digital Design Engineer, Low-Power ASICs

Renesas Electronics; Chandler (AZ); On-site; USD 120,000 - 170,000; Full time

Job summary

Renesas Electronics in Chandler, AZ seeks a Staff Digital Design Engineer to design power- and area-optimized digital circuits for mixed-signal applications. You will interpret requirements to architect low-power digital circuits and support full product lifecycle from concept to mass production, collaborating with Analog and Verification teams.

You will provide technical leadership, mentor juniors, review designs, and help recruit while ensuring the flow from RTL to layout meets timing and

Qualifications

• More than 10 years of digital design experience in areas like wireless handheld, data conversion, and power management.
• Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or related discipline.
• Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design.
• Strong understanding of ASIC design methodology.
• Strong understanding of Lint, CDC & RDC tools.
• Strong understanding of block-level & chip-level verification techniques.
• Strong and proven ability to debug RTL & gate-level simulations.
• Mandatory competence in written and verbal English.
• Willingness to travel domestically or internationally on short notice.
• Ability to work independently and collaboratively.
• Preferred: experience with Digital Signal Processing (DSP) concepts and hardware realizations.
• Preferred: experience with methodology and flow automation using scripting.
• Preferred: experience with mixed-signal design methodologies.
• Preferred: experience developing design constraints and hand-off to P&R.
• Preferred: experience with STA and timing closure.
• Preferred: experience with low-power design techniques including clock and power gating (UPF).
• Preferred: experience with power analysis and optimization.
• Preferred: experience with advanced verification methodologies (UVM).
• Preferred: experience with industry-standard protocols such as AMBA or I2C.

Responsibilities

• Ensuring digital development process is state-of-the-art and meets budget, schedule, and project deliverable goals.
• Designing digital RTL that meets timing, area, power and standards specifications.
• Integrating design at the top level and running block & top-level simulations.
• Participating in Mixed-signal design flow: Micro-architecture, Design partitioning, RTL Verilog/SystemVerilog, Synthesis, Timing Constraints, LINT, CDC, RDC, UPF.
• Working with P&R team to generate layout meeting timing, area, and power requirements.
• Supporting DFT strategy and implementation, and test case development.
• Assisting with top level test-benches and RTL & gate level simulations.
• Collaborating with analog and digital verification engineers on complex test scenarios for pre-silicon verification.
• Supporting AMS, SystemVerilog or Verilog-real behavioral models for analog teams.
• Developing detailed block & chip level design documents and collateral.
• Holding and participating in design reviews and checklists.
• Perform silicon evaluation as required.
• Documenting device errata and engineering changes.

Skills

Digital design

Verilog/SystemVerilog

ASIC design

RTL verification

UVM

English proficiency

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Lint

CDC

RDC

STA

P&R tools

Job description

Renesas Electronics in Chandler, AZ seeks a Staff Digital Design Engineer to design power- and area-optimized digital circuits for mixed-signal applications. You will interpret requirements to architect low-power digital circuits and support full product lifecycle from concept to mass production, collaborating with Analog and Verification teams.

You will provide technical leadership, mentor juniors, review designs, and help recruit while ensuring the flow from RTL to layout meets timing and