Senior Design Verification Engineer (eInfochips Inc)

Towards AI, Inc.; Mountain View (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

A tech company in California is seeking an experienced engineer to develop and scale test benches using SystemVerilog and UVM methodologies. The role requires expertise in ASIC with a minimum of 8 years in the field and proficiency in scripting languages like Perl and Python. Responsibilities include regression activities and collaborating with a team to ensure verification closure. This position is integral to the startup environment, emphasizing customer satisfaction and effective progress reporting.

Qualifications

• Minimum of 8 years of experience in ASIC or a related field.
• Proficiency in scripting languages such as Make, Perl, and Python.
• Experience with verification closure working in a team.

Responsibilities

• Developing and scaling test benches using SystemVerilog and UVM methodologies.
• Performing regression, triage, and coverage closure activities.
• Collaborating with a team to achieve verification closure.

Skills

Perl

Prompt Engineering

UVM

Regression

Electronics

Education

Bachelor's degree in electrical or computer engineering

Master’s Degree in Electrical or Computer Engineering

Tools

SystemVerilog

Make

Python

Job description

Arrow Electronics

Published 28 Mar 2026

Mountain View, CA, USA

Full Time

Role Highlights

• Perl
• Prompt Engineering
• UVM
• Regression
• Startup
• Electronics

Tools, Libraries and Frameworks

• Mountain View
• HTTP

Description

The role involves developing and scaling test benches using SystemVerilog and UVM methodologies. Responsibilities include working with AXI, NOC/Crossbar, and performance aspects of designs. The position requires regression, triage, and coverage closure activities. This work is in a start-up mode with limited documentation and requires collaboration with a team to achieve verification closure.

Required Qualifications and Skills

Candidates require a Bachelor's degree in electrical or computer engineering with a minimum of 8 years of experience in ASIC or a related field. Alternatively, a Master’s Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline is acceptable. The role necessitates verification closure with a team and proficiency in scripting languages such as Make, Perl, and Python. Ensuring customer satisfaction and effectively reporting progress to the customer are also key requirements.