Senior Design Engineer

Bestinfo Systems LLC; Camden (NJ); On-site; USD 115,000 - 140,000; Full time

Job summary

A leading technology firm in Camden, NJ is seeking a Global Delivery Head to lead FPGA/ASIC design for high-speed crypto applications. The ideal candidate will have extensive experience in ASIC/FPGA development, strong analytical skills, and proficiency in VHDL. This role requires collaboration with engineering teams to ensure high-quality designs and successful project execution. Competitive salary and relocation assistance are offered.

Benefits

Relocation Assistance

Best-in-class benefits

Qualifications

• 5+ years of experience in ASIC/FPGA development.
• Proficient with EDA tools and VHDL.

Responsibilities

• Architect and implement high-speed crypto architectures.
• Perform module-level verification and lab debugging.

Skills

VHDL

Analytical Skills

Project Leadership

Education

Bachelor's Degree

MSEE

Tools

Synopsys Synplify

Vivado

Xilinx MPSOC

Job description

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Global Delivery Head BestInfo Systems LLC, Founder & CEO Best Infosystems Ltd

Job Type: Full-Time (FTE)

Location: Camden-NJ

Base Salary: $115,000 to $140,000 + Best-in-class benefits

Relocation Assistance Available: Yes

Job Description:

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for delivering FPGA/ASICs for high-speed crypto applications. S/he will architect and implement high-speed crypto architectures on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands-on design and debugging involving Ethernet, TCP/IP protocols.

Essential Functions:

• Derive engineering specifications from system requirements and develop detailed architecture.
• Execute design (RTL and/or HLS - C++ to RTL) and ensure RTL quality (RDC, CDC, Formal, Lint).
• Generate test plans.
• Perform module-level verification, synthesis/STA, lab debug, and SW-driven validation on Linux-based SoC evaluation boards.
• Silicon/FPGA bring-up, characterization, production ramp/support, and collateral.

Qualifications:

• BSEE, MSEE preferred.
• 5+ years of experience in developing, implementing, and verifying high-performance communications/networking ASIC/FPGA products.
• Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
• Proficient with CDC, RDC, and Formal EDA tools.
• Proficient in VHDL.
• Proficient with Synthesis/PAR tools: SDC, Synopsys Synplify, Vivado.
• Strong logic/board debugging and analytical skills.
• Experience with project leadership and EVM.
• Excellent written, verbal, and presentation skills.

Preferred Additional Skills:

• Proficiency in C++ (OOP).
• Experience with Xilinx MPSOC design, SDKs, BSPs on bare metal/PetaLinux OS.
• Knowledge of PCIe, NVMe, USB protocols.
• Experience with High-Level Synthesis tools (Xilinx Vivado HLS, Mentor Calypto).

Skills and Certifications (required):

• Active clearance.
• VHDL.

Security Clearance Required: Yes

Experience: 5+ to 7 years

Seniority Level: Mid-Senior

Minimum Education: Bachelor's Degree

Screening Questions:

• Do you have an active DoD Security Clearance?
• Do you have FPGA experience?
• Do you have VHDL experience?