Senior Debug Engineer - PCIe/CXL, RAS & Memory

AMD

Santa Clara (CA)

On-site

USD 140,000 - 190,000

Full time

7 days ago
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Job summary

AMD is seeking a Senior Server Systems Debug Engineer to join the Server Customer Engineering team. You will lead root-cause analyses and provide high-quality debug solutions for complex SOC issues, collaborating across global teams to deliver reliable, industry-leading technology.

The role emphasizes silicon and system debugging, customer enablement, and scalable problem solving in a high-visibility environment. Bachelor’s or Master’s in engineering is required.

Qualifications

  • 10+ years of total experience in hardware/software debug and validation.
  • Experience with post-silicon validation methodologies is a plus.
  • Proficient in debugging high-speed interfaces and complex SOC issues.

Responsibilities

  • Work on RAS, PCIe, Memory, MCA, CXL and Micro-Controller related failures with customers to resolve issues.
  • Collaborate with AMD global teams to identify best solutions.
  • Provide validation and debug recommendations for validation, new features and debug questions.
  • Utilize debug tools to narrow down root causes of customer failures.
  • Debug issues from bring-up, validation, and production phases of SOC programs.
  • Engage with software/hardware/design teams and lead cross-team collaborations.

Skills

Python scripting
C++ programming
Debug techniques
X86 microarchitecture
System debugging
Collaboration/leadership

Education

Bachelors or Masters in Computer/Electrical Engineering

Tools

Protocol analyzers
Oscilloscope
JTAG tools
Debug scripts

Job description

AMD is seeking a Senior Server Systems Debug Engineer to join the Server Customer Engineering team. You will lead root-cause analyses and provide high-quality debug solutions for complex SOC issues, collaborating across global teams to deliver reliable, industry-leading technology.

The role emphasizes silicon and system debugging, customer enablement, and scalable problem solving in a high-visibility environment. Bachelor’s or Master’s in engineering is required.

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