Senior CPU Memory Design Engineer - SRAMs & Caches

Intel; Austin (TX); Hybrid; USD 221,000 - 312,000; Full time

Job summary

Intel in Austin, Texas is seeking a highly motivated CPU Memory Design Engineer to design full-custom and compiler-based SRAMs, memory arrays, ROMs, and caches for Intel CPUs and SoCs. You will partner with domain experts across technology development to deliver high-density, low-power memory solutions on advanced CMOS processes.

You will work in a fast-paced, hybrid environment on memory circuit design, characterization, simulations, and PPA optimization, with emphasis on power, performance,

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with 6+ years of experience.
• Master's degree with 5+ years of experience.
• PhD with 2+ years of experience.

Responsibilities

• Technical readiness, memory circuit design, characterization and simulations.
• Cache design, critical path simulations and design of custom blocks to meet Power/Performance/Area constraints.
• Memory path-finding activities and power, performance and area (PPA) optimization.
• Memory bit-cell and complex periphery IC design and automation.
• Memory array/IP design, memory circuit innovation.
• Methodology definition tasks as well as executing project schedules.

Skills

CMOS circuit design

Digital logic optimization

Memory design

VLSI design methodologies

Power/Perf/Area optimization

Education

Bachelor's degree in Electrical/Computer Engineering or STEM

Master's degree

PhD (optional)

Tools

EBB design tools

Job description

Intel in Austin, Texas is seeking a highly motivated CPU Memory Design Engineer to design full-custom and compiler-based SRAMs, memory arrays, ROMs, and caches for Intel CPUs and SoCs. You will partner with domain experts across technology development to deliver high-density, low-power memory solutions on advanced CMOS processes.

You will work in a fast-paced, hybrid environment on memory circuit design, characterization, simulations, and PPA optimization, with emphasis on power, performance,