Senior CPU DFT Engineer with AI-Driven Silicon Validation

Google; United States; On-site; USD 163,000 - 236,000; Full time

Job summary

Google in the United States seeks a CPU DFT Engineer to join our advanced silicon team. This role targets in-person collaboration for CPU DFT development, bringing extensive experience with ATPG, JTAG, BIST, and related DFT flows.

The candidate should have 8+ years in DFT for high-performance IP/SoC, with preferred AI/ML-driven techniques and scripting skills. This is a senior, in-person opportunity in Austin or Mountain View with a strong focus on silicon bring-up and validation.

Qualifications

• 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
• Experience developing, deploying, and supporting DFT flows (ATPG, Logic Vision, BIST, or JTAG).
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field preferred.
• Experience applying AI/ML-assisted DFT design techniques for scaling and physical design closure.
• Experience with scripting in Python, Tcl, or Perl, and data mining for QoR metrics.
• Experience developing novel DFT solutions, silicon bring-up, and validation.
• Knowledge of high-performance, low-power design DFT techniques and end-to-end silicon flows.

Responsibilities

• Partner with cross-functional teams to architect, implement, and verify design-for-test (DFT) solutions for advanced CPU designs.
• Pioneer custom DFT methodologies using industry-standard EDA tools to accelerate turnaround times and test coverage.
• Develop, debug, and optimize production test patterns for automatic test equipment flows to support silicon delivery.
• Mentor peers and foster cross-functional engineering collaboration across the DFT organization.

Skills

Problem solving

Mentoring

Team collaboration

Education

Bachelor's degree in Electrical Engineering or related

Job description

Google in the United States seeks a CPU DFT Engineer to join our advanced silicon team. This role targets in-person collaboration for CPU DFT development, bringing extensive experience with ATPG, JTAG, BIST, and related DFT flows.

The candidate should have 8+ years in DFT for high-performance IP/SoC, with preferred AI/ML-driven techniques and scripting skills. This is a senior, in-person opportunity in Austin or Mountain View with a strong focus on silicon bring-up and validation.