Senior CPU Design Engineer

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 310,500; Full time

Benefits offered by this job

Equity options

Comprehensive benefits package

Job summary

A leading technology company in Santa Clara is seeking a Senior CPU Design Engineer to lead the design of high-performance, low-power CPU subsystems. You will drive the micro-architecture definition, implement RTL, and collaborate with the verification team. Ideal candidates have 8+ years in micro-architecture and RTL development, and strong skills in Verilog/SystemVerilog. The position offers a competitive salary range of $168,000 to $310,500 based on level, experience, and benefits.

Qualifications

• 8+ years of proven experience in micro-architecture and RTL development of complex, high-speed designs, ideally in CPU subsystems.
• Strong exposure to computer architecture and digital systems design.
• Highly proficient in logic design, Verilog/SystemVerilog, with a deep understanding of physical design and VLSI.

Responsibilities

• Drive the micro-architecture definition and documentation of CPU subsystems.
• Implement RTL and coordinate with the verification team.
• Exercise logic design skills to optimize performance and power targets.

Skills

Logic design

Verilog/SystemVerilog

Scripting languages (Perl, Python)

Micro-architecture experience

Communication skills

Education

BS or MS in Electrical Engineering or Computer Engineering

Job description

Senior CPU Design Engineer

The NVIDIA CPU team is looking for motivated engineers with design experience to build high‑performance, low‑power CPUs. As a senior member, you will lead the micro‑architecture definition and RTL implementation of CPU subsystems.

Responsibilities

• Drive the micro‑architecture definition, feasibility studies, and documentation of CPU sub‑systems.
• Implement RTL and coordinate execution with the verification team to ensure the design is functional.
• Exercise logic design skills to optimize and meet performance, timing, and power targets.
• Deliver a synthesis/timing‑clean design while working with the physical design team to ensure routability and physical implementability.
• Support hardware engineering activities including chip floor planning, power/clock distribution, chip assembly, timing closure, power and noise analysis, and back‑end verification.
• Develop flows and tools as necessary to support design activities.

Qualifications

• BS or MS in electrical engineering or computer engineering (or equivalent experience).
• 8+ years of proven experience in micro‑architecture and RTL development of complex, high‑speed designs, ideally in CPU subsystems.
• Exposure to computer architecture and digital systems design.
• Highly proficient in logic design, Verilog and/or SystemVerilog, with a deep understanding of physical design and VLSI.
• Strengths in scripting languages such as Perl and Python.
• Good communication and interpersonal skills.

Compensation & Benefits

Base salary: $168,000 – $264,500 for Level 4, and $196,000 – $310,500 for Level 5. Salary is determined by location, experience, and internal benchmark levels. Eligible for equity and a comprehensive benefits package.

NVIDIA is an equal‑opportunity employer and is committed to fostering a diverse work environment. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.