Senior Circuit Design Engineer, Noise & Timing

NVIDIA AI; Santa Clara (CA); On-site; USD 168,000 - 265,000; Full time

Job summary

NVIDIA is seeking a Senior Circuit Design Engineer to advance digital, mixed-signal and analog circuits across next‑gen products. You will work in a global circuits team, performing transistor‑level analysis and collaborating with cross‑functional groups to improve timing, power, and noise performance.

Leadership and mentoring of junior engineers are expected capabilities. Key requirements include a BSEE with 8+ years experience (MS preferred), deep submicron process know‑how, and hands‑on

Qualifications

• What we need to see includes a BSEE or equivalent, with 8+ years' experience; MS preferred.
• Deep submicron process understanding and digital circuit design techniques.
• Experience with analog/mixed-signal block design (op-amp, ADC, etc.).
• Hands-on Spice simulations, EM/IR analysis, and STA/closure.
• Experience with Spice-based noise analysis, loop stability, AC/DC/transient analysis, Monte Carlo.

Responsibilities

• Participate in cutting edge Processor design in deep submicron technologies.
• Design innovative circuits (digital, semi-custom, mixed-signal) for silicon correlation and noise mitigation.
• Collaborate with cross-functional teams to improve performance and reliability by transistor-level analysis.
• Drive design and physical implementation of digital and/or mixed-signal IPs for voltage and noise sensing.
• Create prototypes of ideas on test chips and deploy across product lines.
• Mentor/technical lead for junior team members.

Skills

Circuit design

Spice simulations

Timing analysis

EM/IR analysis

Noise analysis

Scripting (Perl/Tcl)

Education

BSEE (or equivalent)

MS in Electrical or Computer Engineering

Tools

Spice

EDA tools

Static timing analysis tools

Automation scripting

Job description

NVIDIA is seeking a Senior Circuit Design Engineer to advance digital, mixed-signal and analog circuits across next‑gen products. You will work in a global circuits team, performing transistor‑level analysis and collaborating with cross‑functional groups to improve timing, power, and noise performance.

Leadership and mentoring of junior engineers are expected capabilities. Key requirements include a BSEE with 8+ years experience (MS preferred), deep submicron process know‑how, and hands‑on