Senior C++ Engineer: FPGA RTL Simulation

sifive; Berkeley (CA); On-site; USD 179,000 - 219,000; Full time

Job summary

SiFive is seeking an experienced C++ software engineer to own the application layer of our hardware emulation framework for RISC-V cores. You will work with a small team including FPGA RTL designers, compiler developers, and RISC-V software/hardware engineers to deliver fast, scalable emulation tooling.

Ideal candidates have 7+ years building complete C++ applications, deep knowledge of C++20+ features, and strong concurrency skills.

Qualifications

• BS/MS/PhD in CS/CE/EE
• 7+ years building complete C++ applications with modern C++ features
• Strong understanding of C++ concurrency and multithreaded development
• Self-directed with strong oral and written communication skills

Responsibilities

• Develop the C++ application that is the software component of our hardware emulation framework.
• Collaborate with FPGA RTL designers, compiler developers, and RISC-V software/hardware engineers.
• Ensure high-performance, scalable, multithreaded C++ code for efficient software development and debugging.

Skills

C++

Multithreaded programming

C++20+ features

Concurrency

Strong communication

Education

BS/MS/PhD in CS/CE/EE

Tools

MLIR/LLVM familiarity

FPGA RTL experience

Xilinx FPGAs

Job description

SiFive is seeking an experienced C++ software engineer to own the application layer of our hardware emulation framework for RISC-V cores. You will work with a small team including FPGA RTL designers, compiler developers, and RISC-V software/hardware engineers to deliver fast, scalable emulation tooling.

Ideal candidates have 7+ years building complete C++ applications, deep knowledge of C++20+ features, and strong concurrency skills.