Senior Autonomous Vehicle Performance Engineer

NVIDIA Corporation; Santa Clara (CA); On-site; USD 224,000 - 431,000; Full time

Job summary

NVIDIA in Santa Clara, CA is seeking a Senior Software Performance Engineer for Autonomous Vehicles to optimize latency and throughput of our L2/L3/L4 driving solutions on multi‑computer, heterogeneous hardware.

You will implement high‑performance C++ code with CUDA/GPGPU, collaborate across HW, OS and safety teams, and push the limits of parallel architectures while aligning with MISRA and safety standards.

Qualifications

• MS or PhD in Computer Science, Computer Architecture, Electrical Engineering or related field; or equivalent experience.
• 12+ years of relevant professional experience.
• Excellent C and C++ programming skills.
• Solid understanding of programming and debugging techniques, especially for parallel architectures.
• Good understanding of system software/operating systems and computer architecture.
• Experience with performance analysis, optimizations and benchmarking.
• Outstanding communication and collaboration skills across teams.

Responsibilities

• Develop, maintain and optimize latency and throughput of NVIDIA’s L2/L3/L4 autonomous driving solutions.
• Devise acceleration strategies to improve software architecture on multi-computer heterogeneous HW.
• Develop high-performance product code in C++ using CUDA/ARM NEON while complying with MISRA safety standards.
• Collaborate with HW, product, OS, and safety teams to design next-gen products.

Skills

C/C++ programming

Performance analysis

Parallel architectures

Latency optimization

Collaboration

CUDA/GPGPU

Education

MS or PhD in Computer Science/Computer Architecture/Electrical Engineering

Tools

CUDA

Job description

NVIDIA in Santa Clara, CA is seeking a Senior Software Performance Engineer for Autonomous Vehicles to optimize latency and throughput of our L2/L3/L4 driving solutions on multi‑computer, heterogeneous hardware.

You will implement high‑performance C++ code with CUDA/GPGPU, collaborate across HW, OS and safety teams, and push the limits of parallel architectures while aligning with MISRA and safety standards.