Senior ATE Wafer Test Engineer: Yield & Debug Lead
NOKIA
Sunnyvale (CA)
On-site
USD 100,000 - 130,000
Full time
14 days+
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Job summary
A leading technology company in Sunnyvale is seeking an experienced test engineer to work with automated test equipment (ATE) for analog wafer level IC testing. The candidate should have a BS in Electrical Engineering or Physics and at least 5 years of relevant experience. Responsibilities include interfacing with vendors, tracking production yields, and developing procedures to improve efficiency. The role demands strong analytical, debugging, and communication skills, along with proficiency in various data analysis and programming tools.
Qualifications
5+ years of industrial experience in analog wafer level IC testing.
Experience with probe card cleaning, maintenance, and debug.
Ability to write concise reports and present findings.
Responsibilities
Interface with external vendors for R&D and production testing.
Ensure test software and hardware align with written Test Plan.
Track production yield and milestone assessments.
Support engineering releases through pilot runs.
Develop procedures to improve efficiency and yield.
Skills
Scheduling and planning projects
Automated test equipment (ATE)
Data analysis and interpretation
Scripting and programming
Debugging and critical thinking
Communication skills
Education
BS in Electrical Engineering or Physics
Tools
Galaxy
JMP
Perl
VB
SQL
Perforce
UNIX/Linux
Job description
A leading technology company in Sunnyvale is seeking an experienced test engineer to work with automated test equipment (ATE) for analog wafer level IC testing. The candidate should have a BS in Electrical Engineering or Physics and at least 5 years of relevant experience. Responsibilities include interfacing with vendors, tracking production yields, and developing procedures to improve efficiency. The role demands strong analytical, debugging, and communication skills, along with proficiency in various data analysis and programming tools.