Senior ASIC Physical Design Engineer – Low-Power IP

Qualcomm; Santa Clara (CA); Presencial; USD 135.000 - 202.000; Jornada completa

Descripción de la vacante

Qualcomm Technologies, Inc. in Santa Clara is seeking an ASIC Engineer to define, model, and design IP (block/SoC) for high-performance, low-power products.

The role involves verification, validation, and documentation of IP development, with collaboration across software and hardware teams to meet system requirements. The position emphasizes working across teams, optimizing the design flow from high-level concepts to implementation, and writing comprehensive technical documentation for EDA/IP

Formación

• Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC related work
• Master's degree in Science, Engineering, or related field with 1+ year of ASIC related work
• PhD in Science, Engineering, or related field

Responsabilidades

• Defines, models, designs (digital and/or analog) and verifies IP (block/SoC) development for high-performance, low-power products.
• Creates architectures, circuit specs, logic designs, and system simulations from requirements.
• Collaborates across software and hardware teams to meet system requirements and customer needs.
• Evaluates process flow from high-level design to place-and-route and timing/power analysis.
• Uses RTL to GDS Flow and Virtuoso to enable architecture and design of IP/SoC.
• Writes detailed documentation for EDA/IP/ASIC projects.

Conocimientos

ASIC design experience

ASIC verification

IP development

Educación

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Herramientas

Scripting tools

Programming languages

Design verification methods

Descripción del empleo

Qualcomm Technologies, Inc. in Santa Clara is seeking an ASIC Engineer to define, model, and design IP (block/SoC) for high-performance, low-power products.

The role involves verification, validation, and documentation of IP development, with collaboration across software and hardware teams to meet system requirements. The position emphasizes working across teams, optimizing the design flow from high-level concepts to implementation, and writing comprehensive technical documentation for EDA/IP