Senior ASIC/FPGA Design Engineer – RTL/Verification

Prattwhitney; Cedar Rapids (IA); On-site; USD 87,000 - 165,000; Full time

Benefits offered by this job

Medical insurance

Relocation assistance

Tuition reimbursement

401(k) plan

Job summary

Collins Aerospace, an RTX company, is hiring an experienced FPGA/ASIC Design Engineer in Cedar Rapids, IA, onsite. The role requires a DoD security clearance, STEM degree, and 5+ years in RTL/Verilog/VHDL, with leadership in design and verification.

Responsibilities include architecture, timing closure, testbench development, and using industry tools like ModelSim, Synplify, Quartus, and Vivado. Benefits and relocation support are offered.

Qualifications

• Typically requires a STEM degree and 5+ years of relevant experience; DoD security clearance required.
• U.S. citizenship and ability to obtain/maintain a security clearance required.
• Experience in RTL coding and simulation in Verilog or VHDL.
• Experience in digital circuit architecture, timing analysis, and timing closure.
• Experience in Testbench development for verification of RTL blocks using SystemVerilog.
• Proficient with ASIC/FPGA tools (ModelSim, Synplify, Quartus, Vivado).
• Familiarity with revision control concepts/tools (Git, Subversion).

Responsibilities

• Identify requirements capture, ASIC/FPGA digital architecture and design using RTL, timing closure, verification, and system integration.
• Recommend new tools and practices for continuous improvement in the group’s ASIC/FPGA design flow.
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status.

Skills

RTL coding

SystemVerilog

Digital architecture

Testbench development

Git

Education

STEM degree

Advanced degree

Tools

ModelSim

Synplify

Quartus

Vivado

Git

Job description

Collins Aerospace, an RTX company, is hiring an experienced FPGA/ASIC Design Engineer in Cedar Rapids, IA, onsite. The role requires a DoD security clearance, STEM degree, and 5+ years in RTL/Verilog/VHDL, with leadership in design and verification.

Responsibilities include architecture, timing closure, testbench development, and using industry tools like ModelSim, Synplify, Quartus, and Vivado. Benefits and relocation support are offered.