Senior ASIC Design Verification Engineer - LPU

NVIDIA Gruppe; California (MO); On-site; USD 168,000 - 264,500; Full time

Benefits offered by this job

Generous benefits package

Equity eligibility

Job summary

NVIDIA Gruppe is looking for an ASIC Verification Engineer in California to validate designs for their next-generation inference accelerator. This role involves collaborating with teams to optimize the verification process and utilizing advanced methodologies.

Ideal candidates will have a Bachelor's degree in a related field, extensive industry experience, and a strong background in verification tools like SystemVerilog and UVM. A competitive salary ranging from 168,000 to 310,500 USD is offered depending on experience.

Qualifications

• 8+ years of relevant industry experience required.
• Experience with building block and SoC-level testbenches.
• Experience with random stimulus and functional coverage.

Responsibilities

• Verify the design and implementation of the inference accelerator.
• Implement and optimize automated verification flows.
• Collaborate with architects and designers.

Skills

SystemVerilog

Universal Verification Methodology (UVM)

Debugging skills

Analytical skills

Programming in Perl, Python, or C/C++

Education

Bachelor's Degree in Electrical Engineering, Computer Science, or Computer Engineering

Tools

VCS

Verdi

Job description

NVIDIA is transforming computer graphics, PC gaming, and accelerated computing for more than 25 years, and is now leveraging AI to define the next era of computing. The company seeks to build its next-generation inference accelerator and looks for experts to help deliver high‑performance processors.

Responsibilities

• Verify the design and implementation of the inference accelerator as a key member of the ASIC Verification team.
• Verify the ASIC design, architecture, reference models, and micro‑architecture using advanced verification methodologies.
• Understand unit design and implementation, define verification scope, develop verification infrastructure, and verify design correctness.
• Collaborate with architects, designers, and pre‑ and post‑silicon verification teams to accomplish tasks.
• Implement and optimize automated verification flows to improve productivity and efficiency.
• Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process.

Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience) and 8+ years of relevant industry experience.
• Background with building block and SoC‑level testbenches, strong debugging and analytical skills.
• Experience with random stimulus, functional coverage, assertion‑based verification methodologies and tools.
• Expertise in SystemVerilog and Universal Verification Methodology (UVM).
• Experience with design and verification tools such as VCS, Verdi, or equivalent.
• Background in UPF power verification is a plus.
• Experience with netlist and DFT verification is a plus.
• Programming experience in Perl, Python, or C/C++ is desirable.
• Knowledge of ASIC design flow, from specification to GDS.
• Knowledge of applying machine learning to ASIC verification flow.

Competitive salaries and a generous benefits package. Base salary ranges from 168,000USD to 264,500USD for Level4 and 196,000USD to 310,500USD for Level5, depending on location and experience. Candidates will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse work environment and is a proud equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.