Senior ASIC Design Verification Engineer - LPU

NVIDIA; California (MO); On-site; USD 168,000 - 264,500; Full time

Job summary

A leading tech company in California is seeking an experienced ASIC Verification Engineer to verify designs for their advanced inference accelerator. The role entails collaborating with cross-functional teams, developing verification infrastructure, and applying innovative methodologies. Ideal candidates should have a Bachelor's in EE, CS, or CE, along with 8+ years of experience in verification, strong skills in SystemVerilog and UVM, and familiarity with machine learning applications. Benefits include a competitive salary and equity options.

Qualifications

• 8+ years of relevant industry experience.
• Experience in verification using random stimulus.
• Knowledge of applying machine learning to ASIC verification flow.

Responsibilities

• Verify the design and implementation of the inference accelerator.
• Collaborate with architects and designers.
• Implement and optimize automated verification flows.

Skills

SystemVerilog

UVM

Debugging and analytical skills

Perl/Python

C/C++ programming

ASIC design flow knowledge

Education

Bachelor's Degree in EE, CS or CE

Tools

VCS

Verdi

Job description

Overview

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the design and implementation of the world’s leading inference accelerator. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people around the globe. Their mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality.

Responsibilities

• As a key member of our ASIC Verification team, you will verify the design and implementation of inference accelerator
• You will be responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies
• Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design
• Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks
• Implement and optimize automated verification flows to improve productivity and efficiency
• Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process

Qualifications

• Bachelors Degree in EE, CS or CE (or equivalent experience) and 8+ years of relevant industry experience
• Background with building block and SoC level testbench utilizing strong debugging and analytical skills
• Experience in verification using random stimulus along with functional coverage, assertion-based verification methodologies and tools
• Expertise in SystemVerilog and Universal Verification Methodology (UVM)
• Experience with design and verification tools (VCS, Verdi or equivalent)
• Background in UPF power verification is a plus
• Experience in netlist and DFT verification is a plus
• Perl/Python and C/C++ programming language experience desirable
• Knowledge of ASIC design flow, from specification to GDS
• Knowledge of applying machine learning to ASIC verification flow

Compensation and Benefits

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 16, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.