Senior ASIC AI Engineer for High-Performance GPU Design

Anysilicon; Santa Clara (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Restaurant d'entreprise

Indemnités de stage/alternance

Job summary

NVIDIA is seeking a Senior ASIC AI Engineer to advance GPU design flows by developing high-performance Agentic AI systems that help translate specifications into usable micro-architecture, RTL and physical designs.

You will collaborate with architects, hardware and physical-design engineers to validate AI-driven methods, analyze large datasets with AI agents, and push multi-agent frameworks to improve timing, verification and overall ASIC flow.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related fields with 5+ years of experience, or MS with 3+ years of relevant experience.
• Direct experience with AI-driven development, including coding agents and Agentic workflows.
• Proficiency in AI orchestration tools like LangChain or LlamaIndex and reasoning methodologies.
• Experience with SystemVerilog, RTL, and hardware description languages.
• Understanding of ASIC flow, including RTL, verification, logic synthesis, and timing analysis.

Responsibilities

• Develop AI-powered methods and agents for micro-architecture, RTL, and physical design.
• Use AI agents to analyze datasets and codebases to create reusable skills.
• Evaluate multi-agent frameworks for generating accurate GPU memory designs.
• Collaborate with architects and hardware/physical design teams to meet goals.
• Identify opportunities to integrate AI workflows into existing design processes.

Skills

AI workflows

Agentic development

SystemVerilog

RTL design

Education

Bachelor's degree in Electrical/Computer Engineering or related

Master's degree in Electrical/Computer Engineering or related

Tools

LangChain

LlamaIndex

Job description

NVIDIA is seeking a Senior ASIC AI Engineer to advance GPU design flows by developing high-performance Agentic AI systems that help translate specifications into usable micro-architecture, RTL and physical designs.

You will collaborate with architects, hardware and physical-design engineers to validate AI-driven methods, analyze large datasets with AI agents, and push multi-agent frameworks to improve timing, verification and overall ASIC flow.