Senior Analog Methodology Architect

Synopsys, Inc.

Boxborough (MA)

On-site

USD 180,000 - 280,000

Full time

9 days ago

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Benefits offered by this job

Health benefits
Wellness program
Inclusive culture
Accommodations available

Job summary

Synopsys, Inc. in the United States is seeking an experienced Analog Methodology Engineer to drive cross-domain workflow improvements, from circuit-to-layout to silicon-to-lab correlation, across mixed-signal IP programs.

You will lead customer engagements, coordinate with foundries, and shape methodology strategies for application-optimized IP and special-purpose silicon. A strong background in transistor-level design, reliability, and STA is essential.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar technical field.
  • 25–30 years in IC design with a BSEE, or 22–25 with an MSEE/PhD.
  • Expert knowledge of analog and adjacent-domain methodologies in cross-domain workflows.

Responsibilities

  • Provide clear ownership for analog and adjacent-domain methodology areas.
  • Act as focal point for customer-driven methodology requirements and integration challenges.
  • Be accountable for prioritization, adoption, stakeholder engagement, and execution.
  • Improve coordination across product teams and organizations, including customers and foundries.
  • Support methodology for application-optimized IP and special-purpose silicon projects.

Skills

Analog methodology
Circuit-to-layout
Scripting
AI/ML in analog

Education

Bachelor's degree in Electrical Engineering
MS EE or PhD preferred

Tools

Python

Job description

Synopsys, Inc. in the United States is seeking an experienced Analog Methodology Engineer to drive cross-domain workflow improvements, from circuit-to-layout to silicon-to-lab correlation, across mixed-signal IP programs.

You will lead customer engagements, coordinate with foundries, and shape methodology strategies for application-optimized IP and special-purpose silicon. A strong background in transistor-level design, reliability, and STA is essential.

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