Senior Analog Design Engineer

Cypress HCM; Agoura Hills (CA); Hybrid; USD 130,000 - 180,000; Full time

Job summary

A leading company in semiconductor manufacturing is seeking a Mid-Senior Level Analog Design Engineer to design and develop innovative products. The role involves high-speed circuit design, mentoring junior engineers, and collaborating in a dynamic R&D environment. Competitive compensation package includes base salary, bonuses, and stock options.

Benefits

Medical insurance

Vision insurance

401(k) plan with company match

Employee stock purchase plan

Relocation assistance

Qualifications

• 5+ years of experience in analog, high-speed circuit design.
• Experience with high-speed PLL circuits required.

Responsibilities

• Designing and developing new products in R&D.
• Owning analog designs at the chip and/or block level.
• Documenting analysis/simulation to show design achieves critical specifications.

Skills

Analog Circuit Design

High-Speed Circuit Design

Verilog

MATLAB

Job description

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This range is provided by Cypress HCM. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$130,000.00/yr - $180,000.00/yr

Additional compensation types

Annual Bonus and RSUs

Location: Agoura Hills, CA 91301

Hybrid Remote: 3 days in the office per week | Reporting To: Sr. Director, Engineering

Responsibilities:

• Designing and developing new products in a dynamic, R&D organization
• Owning analog designs at the chip and/or block level
• Defining architectures to achieve competitive product specifications
• Designging, simulate, and characterizing high-performance and high-speed circuits
• Creating high-level model design for tradeoff analysis and behavior modeling for verification
• Developing floorplan, working to demonstrate post-extraction performance
• Documenting analysis/simulation to show design achieves critical electrical, timing, and pre-silicon verification flow
• Mentoring junior team members as needed

Requirements:

• 5+ years of professional experience in analog, high-speed circuit design and engineering
• Experience with high-speed PLL circuits is required for this position
• Preference for candidates with experience with transmitter, receiver (CTLE, DFE), DLL, PI, and/or clock distribution circuits
• 2+ years of experience in CMOS analog circuit design, knowledge of bias, op-ramp, LDO
• Experience designing memory interfaces such as DDR4, DDR5, or PCIE
• Experience with Verilog-A, Verilog, or MATLAB is preferred
• Experience with FinFET process and digitally assisted design is preferred
• Competitive medical, dental, vision, and life insurance plans – including HSA and FSA options
• 401K plan with company match
• Employee stock purchase plan (15% discount)
• Relocation assistance

Compensation:

• $130K - $180K + Bonus + RSUs

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering, Information Technology, and Design

• Industries

  Semiconductor Manufacturing and Computer Hardware Manufacturing

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Inferred from the description for this job

Medical insurance

Vision insurance

401(k)

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