Senior AMS Program Manager - Silicon Tape-out Leader

Astera Labs; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs in San Jose, CA is seeking a Principal Engineering Program Manager to lead AMS IP programs from concept through tape-out and bring-up. You will orchestrate multi-disciplinary teams across design, verification, layout, and silicon validation to deliver high-performance IP on schedule and within budget.

This high-impact leadership role requires 8+ years in semiconductor program management, strong stakeholder skills, and experience with ASIC/IC lifecycles.

Qualifications

• Bachelor's degree or higher in a technical field is required.
• 8+ years of experience in program or project management for semiconductor/hardware.
• Proven track record delivering complex silicon/AMS/IP programs through tape-out.

Responsibilities

• Define, drive, and maintain end-to-end schedules for AMS IP development from spec to tape-out and validation.
• Manage critical path, milestones, and dependencies across design, layout, verification, and bring-up.
• Track budgets, deliverables, and program metrics to ensure high-quality outcomes.
• Partner with AMS design, digital, systems, product, and operations teams to align priorities and resolve blockers.
• Lead program reviews, communicate status and risks to leadership and stakeholders.
• Coordinate with foundries, vendors, and external partners on tape-out readiness and schedule commitments.
• Identify, quantify, and mitigate risks across concurrent programs and drive process improvements.

Skills

Program management

Stakeholder management

Cross-functional leadership

AMS/IP programs

Communication

Education

Bachelor's degree in Electrical Engineering or related

Tools

Microsoft Project

Microsoft 365

Job description

Astera Labs in San Jose, CA is seeking a Principal Engineering Program Manager to lead AMS IP programs from concept through tape-out and bring-up. You will orchestrate multi-disciplinary teams across design, verification, layout, and silicon validation to deliver high-performance IP on schedule and within budget.

This high-impact leadership role requires 8+ years in semiconductor program management, strong stakeholder skills, and experience with ASIC/IC lifecycles.