Senior AMS IC Layout Engineer — Remote

SiliconBrite Technologies Inc.; San Jose (CA); Hybrid; USD 150,000 - 210,000; Full time

Benefits offered by this job

Remote-friendly

Job summary

Silicon Brite Technologies Inc. seeks an experienced layout engineer to perform analog and mixed-signal IC layout using Cadence Virtuoso. The role covers design of chip layouts, verification and parasitic extraction for AMS circuits, from blocks to full-chip level.

The ideal candidate has a BS in EE, 15+ years in semiconductors, and strong Cadence tool knowledge. Remote work is available globally, with base in San Jose, CA preferred.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• At least 15 years of direct experience working with semiconductor companies.
• Good understanding of the Cadence EDA toolset.
• Basic knowledge of AMS circuits is preferred.
• Strong analytical and communication skills.
• Self-starter and excellent team player.

Responsibilities

• Design of chip layout and complete set of design verification for various analog mixed-signal circuits (individual blocks to full-chip level).
• Manage in-house developed IP library and optimization of layout implementation techniques.
• Solid knowledge of Physical verifications, debug, and parasitic extractions including LVS/DRC.
• Analyze and review floor planning/schematics with responsible IC designers.

Skills

AMS circuits knowledge

Analytical skills

Communication skills

Team player

Self-starter

Education

B.S. in Electrical Engineering

Tools

Cadence EDA tools

Cadence Virtuoso

Job description

Silicon Brite Technologies Inc. seeks an experienced layout engineer to perform analog and mixed-signal IC layout using Cadence Virtuoso. The role covers design of chip layouts, verification and parasitic extraction for AMS circuits, from blocks to full-chip level.

The ideal candidate has a BS in EE, 15+ years in semiconductors, and strong Cadence tool knowledge. Remote work is available globally, with base in San Jose, CA preferred.