Senior AI/ML Accelerator Digital Design Engineer

Qualcomm; Austin (TX); On-site; USD 140,000 - 200,000; Full time

Job summary

Qualcomm seeks a Senior AI/ML Logic Design Engineer to architect and implement advanced digital logic blocks for wireless and multimedia SoCs. You will design, verify, and optimize ML accelerators and DSP‑centric hardware in cutting‑edge process nodes, focusing on low power, high performance, and area efficiency.

Responsibilities include RTL design, micro‑architecture, synthesis, timing closure, and collaboration with verification and physical design teams.

Qualifications

• Experience designing RTL for ML accelerators or DSP blocks.
• Strong background in digital logic design and verification.
• Familiarity with timing closure and synthesis flows.

Responsibilities

• Architect and implement digital logic blocks for AI/ML workloads.
• Collaborate with verification and physical design teams to deliver chips.

Skills

RTL design

ML accelerators

DSP hardware

Low power design

Team leadership

Job description

Qualcomm seeks a Senior AI/ML Logic Design Engineer to architect and implement advanced digital logic blocks for wireless and multimedia SoCs. You will design, verify, and optimize ML accelerators and DSP-centric hardware in cutting‑edge process nodes, focusing on low power, high performance, and area efficiency. Responsibilities include RTL design, micro‑architecture, synthesis, timing closure, and collaboration with verification and physical design teams. You will guide junior engineers, influence chip architecture, and help bring next‑generation 5G, AI, and edge computing products to market in a fast‑paced, innovation‑driven environment.