Senior AI Accelerator Module Design Engineer (Equity)

Meta; Santa Clara (CA); On-site; USD 173,000 - 245,000; Full time

Job summary

Meta HDRTP is seeking a senior AI Accelerator Module Design Engineer to own the electrical and PCB design of accelerator modules powering MTIA and other AI accelerators. You will define module requirements with cross-functional teams and lead ASIC package-to-board co-design, power delivery, high-speed interfaces, and design-for-manufacturability.

This is a senior IC/PCB leadership role with broad cross-domain impact.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related technical discipline.
• 10+ years of experience in electrical and PCB design for high-speed, high-power digital systems (servers, accelerators, networking, or HPC)
• Demonstrated experience as the lead engineer taking multiple complex custom board or module designs from concept through volume production
• Expert-level proficiency with EDA tools for schematic capture and PCB design (Cadence Allegro/OrCAD, Altium Designer, or equivalent)
• Deep expertise in high-speed digital interface design (PCIe, CXL, DDR4/DDR5, HBM, Ethernet 25G–800G) and SerDes-based channel design, including stackup and channel budgeting trade-offs
• Deep expertise in power delivery network architecture for high-current loads, including DC-DC topology selection, transient and efficiency analysis, and plane/decoupling strategy
• Experience with ASIC or GPU package-to-board co-design and breakout routing for high pin-count devices
• Experience leading board and silicon bring-up, debug, and failure analysis using oscilloscopes, VNAs, TDR, and power analyzers
• Experience owning technical direction across multiple concurrent programs and influencing decisions across hardware, firmware, mechanical, thermal, and manufacturing organizations
• Experience driving external ODM/JDM or component partners through design and production cycles
• Experience communicating technical trade-offs and recommendations in writing and verbally to engineering leadership

Responsibilities

• Own the end-to-end electrical architecture and PCB design of AI accelerator modules for high-performance, high-power, high-efficiency custom silicon (MTIA) and third-party accelerators
• Define module requirements and specifications in partnership with ASIC, platform, rack, and systems architecture teams
• translate system-level targets into implementable board-level design intent
• Lead ASIC package-to-board co-design, including breakout routing strategy, substrate and interposer interaction, and escape feasibility analysis for high pin-count, high-bandwidth devices
• Architect power delivery networks for extreme-current loads (multi-hundred-amp rails), owning DC-DC topology and architecture trade-offs (performance, transient response, efficiency, area, cost), decoupling strategy, and plane/stackup partitioning
• Drive high-speed interface design across PCIe Gen5/Gen6, CXL, UCIe, DDR5/LPDDR, HBM, NVLink/scale-up fabrics, and Ethernet up to 800G, including simulation-guided stackup and channel budgeting
• Set the technical direction for SI/PI methodology in partnership with Signal and Power Integrity teams
• define correlation strategy between simulation and measured silicon
• Define and own module-level design reviews
• set the quality bar for schematic, layout, and DFM/DFT readiness across internal designs and ODM-executed designs
• Lead board and silicon bring-up and own root-cause analysis of the most complex electrical, power, and interoperability failures
• drive corrective design action to closure
• Drive ODM/JDM partners through full NPI-to-mass-production cycles, holding partners to Meta design standards and schedule
• Develop reusable reference designs, design-rule libraries, and design automation that scale across programs and generations
• publish and champion designs through the Open Compute Project
• Evaluate and qualify leading-edge technologies with industry partners — HDI and advanced substrates, embedded components, novel materials, co-packaged and coherent optics — and build the business case for adoption
• Identify cross-organizational problems and lead XFN efforts to resolution without being asked
• influence decisions outside your direct scope through technical credibility rather than authority
• Mentor and develop PCB/module design engineers
• contribute to hiring, calibration of technical standards, and team-wide best practices

Skills

Electrical design

PCB design

High-speed interface design

Power delivery networks

Signal integrity

Team mentorship

Engineering leadership

System-level architecture

Education

BS in Electrical Engineering

MS/PhD preferred

Tools

Cadence Allegro/OrCAD

Altium Designer

HFSS/Sigrity

Job description

Meta HDRTP is seeking a senior AI Accelerator Module Design Engineer to own the electrical and PCB design of accelerator modules powering MTIA and other AI accelerators. You will define module requirements with cross-functional teams and lead ASIC package-to-board co-design, power delivery, high-speed interfaces, and design-for-manufacturability.

This is a senior IC/PCB leadership role with broad cross-domain impact.