Layout Engineer

IC Resources; Maryland; On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Competitive compensation

Equity

Annual performance bonus

Comprehensive benefits

Job summary

IC Resources in College Park, Maryland, is seeking a Photonic Layout Engineer to join its hardware design team. You will lead the layout and tape-out of Photonic Integrated Circuits (PICs) for quantum hardware contexts.

You will apply Python-based workflows to generate GDS layouts, verify with DRC/LVS, and contribute to PDK development while coordinating with design, fabrication and test teams to ensure manufacturability. This role offers competitive compensation and equity.

Qualifications

• Hands-on PIC layout experience required.
• Experience moving photonic layouts to fabrication.
• 2+ years Python for photonic mask/layout.
• Familiar with DRC/LVS and layout-rule driven design.
• Degree in Photonics/Physics/EE or equivalent.

Responsibilities

• Develop and own layouts for complex Photonic Integrated Circuits (PICs).
• Arrange and route photonic components across multi-layer chip designs.
• Account for electrical, metal and CMOS routing constraints during photonic layout.
• Generate large-scale GDS / mask layouts using Python-based design workflows.
• Support chip and reticle-level layout through foundry tape-out.
• Perform layout verification including DRC and LVS.
• Contribute to the development and maintenance of custom photonic PDKs.
• Work with photonic designers to integrate components including waveguides, splitters and couplers.
• Collaborate with fabrication, test and packaging teams to establish design rules.
• Document layout methodologies and final tape-out files.

Skills

PIC layout

Python scripting

DRC/LVS

Education

Photonics/Physics/EE degree

Tools

gdsfactory

Luceda IPKISS

KLayout

Job description

We are working with a leading quantum technology company looking to hire a Photonic Layout Engineer to join its hardware design team in College Park, Maryland.

This is a highly technical, hands-on position focused on the layout and tape-out of complex Photonic Integrated Circuits (PICs) used within next-generation quantum hardware.

You will work closely with photonic designers, scientists, fabrication engineers, test engineers and packaging teams to translate photonic designs into manufacturable chip layouts.

A major focus of the position will be programmatic photonic layout using Python, alongside layout verification, PDK development and foundry tape-out.

What You'll Be Doing

• Develop and own layouts for complex Photonic Integrated Circuits (PICs)
• Arrange and route photonic components across multi-layer chip designs
• Account for electrical, metal and CMOS routing constraints during photonic layout
• Generate large-scale GDS / mask layouts using Python-based design workflows
• Support chip and reticle-level layout through foundry tape-out
• Perform layout verification including DRC and LVS
• Contribute to the development and maintenance of custom photonic PDKs
• Work with photonic designers to integrate components including waveguides, splitters, couplers and other passive/active photonic structures
• Collaborate with fabrication, test and packaging teams to establish design rules and manufacturability requirements
• Document layout methodologies, design rules and final tape-out files

What We're Looking For

• Strong hands-on experience with PIC layout
• Experience taking photonic layouts toward fabrication or tape-out
• At least 2 years of experience using Python for photonic mask/layout generation
• Experience with tools such as gdsfactory, Luceda IPKISS, KLayout, or similar programmatic layout environments
• Understanding of common photonic components such as waveguides, beamsplitters, grating couplers and related structures
• Experience with DRC, LVS and design-rule-driven layout
• Degree in Photonics, Physics, Electrical Engineering or a related discipline, or equivalent industry experience
• Ability to work across photonic design, fabrication and engineering teams

Particularly Valuable Experience

• Photonic PDK development
• Reticle or full-chip layout
• Complex semiconductor or multi-layer chip integration
• Foundry design rules and manufacturing processes
• Cadence, Synopsys or Ansys environments

Why Consider It?

This is an opportunity to work on highly advanced integrated photonic hardware at the intersection of photonics, semiconductor technology and quantum computing.

You'll have direct involvement in bringing new chip designs from engineering requirements through layout, verification and commercial foundry tape-out, with your work contributing directly to the scaling of next-generation quantum systems.

Competitive compensation, equity, annual performance bonus and comprehensive benefits are available.