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New Grad in San Jose, CA seeks an intern to develop and validate IP-level power macromodels for AI memory components. You will extract power features from RTL, SystemC, and C simulations and calibrate models using synthesis, circuit-level references, and measured data.
Ideal candidates are MS or PhD students in Electrical Engineering, Computer Science, or related fields with proficiency in Verilog, SystemVerilog, SystemC, C++, or Python, and at least one academic term remaining.