RTL Power Macromodeling Intern for AI Memory

Samsung; San Jose (CA); On-site; USD 39,000 - 94,000; Full time

Benefits offered by this job

Relocation stipend

Housing stipend

Job summary

New Grad in San Jose, CA seeks an intern to develop and validate IP-level power macromodels for AI memory components. You will extract power features from RTL, SystemC, and C simulations and calibrate models using synthesis, circuit-level references, and measured data.

Ideal candidates are MS or PhD students in Electrical Engineering, Computer Science, or related fields with proficiency in Verilog, SystemVerilog, SystemC, C++, or Python, and at least one academic term remaining.

Qualifications

• MS or PhD student in Electrical Engineering, Computer Science, or related fields.
• Proficiency in Verilog, SystemVerilog, SystemC, C++, or Python.
• Knowledge of CMOS dynamic and leakage power and circuit abstraction.
• Must have at least one academic term remaining.

Responsibilities

• Develop and validate IP-level power macromodels for AI memory components.
• Extract power features from RTL, SystemC, and C simulations.
• Calibrate models using synthesis, circuit-level references, and measured data.
• Integrate validated models into trace-driven power and thermal simulators.

Skills

Verilog

SystemVerilog

SystemC

C++

Python

Education

MS or PhD student in Electrical Engineering, Computer Science, or related fields

Job description

New Grad in San Jose, CA seeks an intern to develop and validate IP-level power macromodels for AI memory components. You will extract power features from RTL, SystemC, and C simulations and calibrate models using synthesis, circuit-level references, and measured data.

Ideal candidates are MS or PhD students in Electrical Engineering, Computer Science, or related fields with proficiency in Verilog, SystemVerilog, SystemC, C++, or Python, and at least one academic term remaining.