RTL Design & FPGA Integration Engineer – Hybrid

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Advanced Micro Devices, Inc. in San Jose seeks a Senior FPGA/RTL design engineer to drive high-performance silicon, leveraging RTL design methodologies, AI-assisted automation, and modern EDA tools. You will collaborate across time zones with architects, HW and SW teams to deliver next-gen FPGA products.

The role emphasizes cross-functional execution, verification, and timely delivery of IP features, with a focus on PPA optimization and integration within the AECG group.

Qualifications

• Bachelor’s or Master’s in Computer Engineering or Electrical Engineering.
• RTL design (Verilog/SystemVerilog) and digital/analog block implementation.
• Understanding of VLSI design flow from RTL through Physical Design and GDSII.
• Familiarity with Physical Implementation: floorplanning, synthesis, P&R, STA.
• Experience with EDA tools: Design Compiler, Primetime, VCS, Cadence Virtuoso.
• Knowledge of UVM/OVM verification, simulation environments, debugging.

Responsibilities

• Collaborate with architects, hardware and SW-FW engineers to define product requirements and IP features.
• Build early-stage RTL designs based on product intent guiding Silicon and Solution co-development.
• Build and enhance AI-driven infrastructure to accelerate IP integration and timelines.
• Apply data-driven methods to align engineering across next-gen products and nodes.
• Support functional simulation and software quality checks with robust verification coverage.
• Partner with global teams to ensure seamless integration and delivery.

Skills

RTL design

Verilog/SystemVerilog

VLSI flow

EDA tools

UVM/OVM

FPGA arch

Scripting

Education

Bachelor’s or Master’s in Computer or Electrical Engineering

Tools

Synopsys Design Compiler

Primetime

VCS

Cadence Virtuoso

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE

As a key member of AMD’s FPGA Product development team, you will have various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from conception & planning to productization. You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting PPA, cost and schedule optimized Silicon implementation and first-time-right SW solution.

THE PERSON

You are passionate about HW architecture, Digital design, and building cutting-edge silicon. As a strong problem solver and analytical thinker, you bring collaboration, communication, and adaptability to cross-functional teams spanning multiple time zones.

KEY RESPONSIBILITIES

• Collaborate with architects, hardware engineers, and SW-FW engineers to understand the product requirements and IP features.
• Build early-stage RTL designs based on product and architecture intent driving Silicon and Solution co-development.

• Build and enhance AI-driven infrastructure to accelerate IP integration and improve development timelines.
• Apply data-driven methodologies to align engineering teams across next-generation products and technology nodes.
• Support functional simulation and software quality checks, ensuring robust verification coverage.
• Partner with global teams to achieve seamless integration and delivery.

PREFERRED EXPERIENCE

• This is NOT a New/Recent College Grad-level position; Targeting background expertise in RTL design (Verilog/SystemVerilog), including digital/analog block implementation.
• Understanding of VLSI design flow, from RTL through Physical Design and GDSII.
• Familiarity with Physical Implementation processes: floorplanning, synthesis, P&R, STA.
• Experience with EDA tools (Synopsys Design Compiler, Primetime, VCS; Cadence Virtuoso).
• Knowledge of UVM/OVM verification, simulation environments, and debugging.
• Understanding of FPGA architecture and usage models is a plus.
• Proficiency in scripting (Perl, Tcl, Python, Shell) for design automation.
• Excellent communication skills and ability to thrive in a fast-paced, global environment.

ACADEMIC QUALIFICATIONS

• Bachelor’s or Master’s in Computer Engineering or Electrical Engineering.

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.