RTL Design Engineer — SoC & Low-Power Expert

Battelle; Columbus (OH); Híbrido; USD 86.000 - 123.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Hybrid work model

PTO and flexible schedule

401(k) with company match

Tuition assistance

Wellness benefits

Descripción de la vacante

Battelle's Advanced Microsystem Solution Business Line seeks an RTL Design Engineer in Columbus, Ohio to design and implement advanced digital ICs/SoCs. You will develop microarchitectures, implement RTL, and optimize for performance, power, and area, working with verification, physical design, and system engineering teams.

The ideal candidate has Verilog/SystemVerilog experience, RTL synthesis and timing analysis skills, and a passion for modern SoC development flows for high-performance

Formación

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of RTL design experience.
• Strong Verilog/SystemVerilog RTL design experience.
• Deep understanding of digital design fundamentals and computer architecture.
• Microarchitecture design and optimization experience.
• Knowledge of synthesis, timing analysis, and STA.
• Experience with EDA tools (Synopsys, Cadence, Siemens).
• Understanding of low power design techniques and power optimization.
• Experience with clock domain crossing (CDC).
• Scripting skills (Python, TCL) for design automation.
• Knowledge of DFT concepts and Git.
• US Citizenship and ability to obtain security clearance.

Responsabilidades

• Design and implement RTL code for digital blocks and subsystems.
• Develop microarchitecture specifications and design documents.
• Optimize designs for performance, power, and area (PPA).
• Perform RTL synthesis and timing closure.
• Collaborate with verification engineers for quality and coverage.
• Debug design issues during verification and silicon validation.
• Participate in design reviews and provide guidance.
• Create and maintain design documentation and specs.
• Implement DFT structures.
• Assist with timing constraints and floor planning with the physical design team.
• Analyze and resolve CDC and lint violations.

Conocimientos

RTL design

Verilog

SystemVerilog

Synthesis

Timing analysis

Low power

SoC development

CDC

Python

Git

DFT

US Citizenship

Security clearance

EDA tools

Educación

Bachelor's or Master's in Electrical/Computer Eng

Herramientas

Synopsys

Cadence

Siemens

Descripción del empleo

Battelle's Advanced Microsystem Solution Business Line seeks an RTL Design Engineer in Columbus, Ohio to design and implement advanced digital ICs/SoCs. You will develop microarchitectures, implement RTL, and optimize for performance, power, and area, working with verification, physical design, and system engineering teams.

The ideal candidate has Verilog/SystemVerilog experience, RTL synthesis and timing analysis skills, and a passion for modern SoC development flows for high-performance