RTL Design Engineer

TATA ELXSI; United States; On-site; USD 110,000 - 190,000; Full time

Job summary

Tata Elxsi in the United States seeks an experienced RTL design engineer to contribute to digital IPs and subsystem micro-architecture. You will design and verify RTL using Verilog/SystemVerilog and collaborate across teams to ensure high-quality SoC delivery.

The role emphasizes design-for-test, synthesis readiness, and collaboration with verification teams, with opportunities to influence FPGA prototyping and silicon bring-up as needed.

Qualifications

• Strong proficiency in Verilog/SystemVerilog RTL coding.
• Understanding of digital design fundamentals such as FSMs, pipelining, clock-domain crossing, and timing concepts.
• Experience in ASIC/FPGA design and development flows.
• Knowledge of synthesis, timing analysis, lint, and CDC tools.
• Strong debugging and problem-solving skills.

Responsibilities

• Analyze specifications and develop micro-architecture for digital IPs and subsystems.
• Design and implement RTL using Verilog/SystemVerilog.
• Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.
• Support SoC/IP integration activities.
• Participate in design reviews and technical discussions.
• Collaborate with verification teams to resolve design issues and achieve quality sign-off.
• Support FPGA prototyping and silicon bring-up activities as required.
• Prepare and maintain design documentation.

Skills

Verilog/SystemVerilog RTL coding

Digital design fundamentals

ASIC/FPGA design

Synthesis/timing/CDC lint tools

Debugging & problem-solving

Job description

Opportunities unlimited for everyone — be bold, curious, and seek to shape the future. At Tata Elxsi, You Matter!

Tata Elxsi works with leading OEMs and suppliers in the automotive & transportation industries for R&D, Design and Product Engineering Services, from architecture to launch and beyond. We accelerate development and testing of connected autonomous and electric vehicles and off-highway systems.

Responsibilities

• Analyze specifications and develop micro-architecture for digital IPs and subsystems.
• Design and implement RTL using Verilog/SystemVerilog.
• Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.
• Support SoC/IP integration activities.
• Participate in design reviews and technical discussions.
• Collaborate with verification teams to resolve design issues and achieve quality sign-off.
• Support FPGA prototyping and silicon bring-up activities as required.
• Prepare and maintain design documentation.

Required Skills

• Strong proficiency in Verilog/SystemVerilog RTL coding.
• Good understanding of digital design fundamentals, FSMs, pipelining, clock-domain crossing, and timing concepts.
• Experience in ASIC/FPGA design and development flows.
• Knowledge of synthesis, timing analysis, lint, and CDC tools.
• Strong debugging and problem-solving skills.