RTL Design Engineer

Snowcap Compute Inc.; San Francisco (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Relocation assistance

On-site work environment

401(k)

Job summary

Snowcap Compute is seeking an experienced RTL engineer to own blocks from microarchitecture to synthesizable Verilog/SystemVerilog. You will write unit tests, respond to lint/CDC checks, and drive synthesis decisions with the back‑end team to meet timing and area constraints.

You will collaborate closely with the microarchitect, DV, and implementation teams in a flat, matrixed environment, ensuring clean, testable RTL that can ship in silicon.

Qualifications

• Strong Verilog and SystemVerilog coding skills with production‑quality RTL experience.
• Deep understanding of synthesizable constructs and their impact on area, timing, and power.
• Fluency with logic synthesis tools (DC/Genus) and reading timing/QoR reports.
• Habits of a designer who works well with verification: testable RTL and parameterization.
• Familiarity with lint, CDC, and static checks and delivering clean RTL.
• Comfort in early‑stage environments where the spec is evolving.

Responsibilities

• Code synthesizable Verilog/SystemVerilog RTL from microarchitecture specs.
• Write block‑level unit tests and assist DV testbench development.
• Run lint, CDC, and static checks on blocks and address issues.
• Drive synthesis and interpret QoR, adjusting RTL for timing and area.
• Participate in code reviews and architecture walkthroughs.
• Collaborate with implementation to resolve synthesis and timing in RTL.
• Push back on specs when needed and propose workable alternatives.
• Set RTL coding standards and conventions for team consistency.

Skills

Verilog/SystemVerilog

RTL design

lint & CDC checks

Synthesis QoR analysis

Formal verification

PCL/SFQ logic familiarity

Tools

Synopsys DC

Cadence Genus

Job description

About the Role

Snowcap is taking a superconducting chip architecture from specification to silicon. The microarchitecture team writes the spec; the RTL is where that spec becomes something the implementation team can route. The logic family is not CMOS, the timing assumptions are not CMOS, and the conventional "code it and let synthesis sort it out" reflex will not survive contact with this design. This role owns the RTL.

You will take microarchitecture specifications and produce synthesizable, well-structured Verilog and SystemVerilog. You will own your block at the implementation level — lint clean, CDC clean, with the testability hooks the verification team needs and the structural choices the back‑end team can actually close on. You will work directly with the Microarchitect, Design Verification, and the implementation team, in a flat, matrixed organization. The expectation is software‑engineer ownership: you write the code, you write the unit tests around it, and you defend the block when it comes back from synthesis or DV with a problem.

In twelve months, the blocks you authored should be the ones the rest of the team trusts on regression and the ones implementation teams do not have to rewrite to close timing. The RTL conventions you set — coding style, file structure, parameterization, assertion discipline — become the baseline every future RTL engineer at Snowcap inherits.

What You'll Own

• Code synthesizable Verilog and SystemVerilog RTL from microarchitecture specifications — your block, your code, your responsibility from spec to clean implementation.
• Write block-level unit tests and assist with DV testbench development around your blocks. The first proof that your RTL does what the spec says is yours, not the verification team’s.
• Run and respond to lint, CDC, and basic static checks on every block you author — clean is the baseline, not the goal.
• Drive synthesis on your blocks and interpret the QoR — read the timing reports, understand the area and power tradeoffs, and revise the RTL when the data argues back.
• Participate in code reviews and architecture walkthroughs — both giving and receiving real critique, in a team small enough that you will see every block.
• Work directly with the implementation team to resolve synthesis and timing issues at the RTL level, including the PCL‑specific cases where standard CMOS coding patterns break.
• Push back on the microarchitecture spec when an implementation reality says it cannot be built as written — and produce the alternative that can.
• Set the RTL coding and structural standards at Snowcap — style, parameterization, assertion use, and the conventions that make a block readable to the next engineer who has to touch it.

What We Need to See

• Strong Verilog and SystemVerilog coding skills with a track record of production‑quality RTL on chips that taped out and ran the workload they were designed for.
• Deep, working understanding of synthesizable constructs and their consequences for area, timing, and power — not just what compiles, but what implements well.
• Fluency with logic synthesis tools — Synopsys DC, Cadence Genus, or equivalent — and the discipline to read timing reports and synthesis QoR data and act on them.
• Habits of a designer who works well with verification: testable RTL, structural assertions, parameterization, and code that is straightforward to wrap a testbench around.
• Working knowledge of lint, CDC, and static checking flows — and the discipline to deliver clean RTL, not waivers‑and‑promises RTL.
• Comfort operating in an early‑stage environment where the spec is still being written, the flow is still being stood up, and "we don't have a template for that yet" is a frequent answer.

Ways to Stand Out

• Span from microarchitecture into RTL — you can read the spec, push back on it intelligently, and code the block that proves the argument. Candidates who genuinely cover both abstractions are weighted heavily.
• Deep RTL specialist track record — chips, protocols, and IP where your RTL was the production version, including memory subsystems, MAC/PCS, high‑speed interconnect, or comparable complexity.
• Experience with custom or non‑standard logic families — asynchronous, wave‑pipelined, or high‑speed custom logic where CMOS coding patterns had to be re‑derived.
• Background at AMD, NVIDIA, Apple, Qualcomm, or comparable silicon teams in the senior or principal RTL band, with shipped silicon to point to.
• Track record of authoring RTL coding standards, internal IP, or reusable design infrastructure that other teams have actually adopted.
• Familiarity with formal verification, equivalence checking, and assertion‑driven design — the techniques that catch bugs in the RTL before the verification team has to.
• Familiarity with superconducting digital logic — PCL, SFQ, AQFP, RSFQ, or related — at any level. We do not require it; we will weight it when we find it.

The Environment

Snowcap is a small, technically elite team writing RTL for a logic family that has not been productized at scale. You will not be one of fifty RTL engineers on a derivative chip. You will be one of a handful, and the blocks you author will not have a previous‑generation reference design sitting next to them.

We are a flat, matrixed organization. You will work daily with the microarchitect, design verification, and the implementation team — directly, without layers. When your block lights up an unexpected timing path or your testbench finds a real bug, that conversation happens in the room that day, not three sprints from now.

This role is on‑site at our San Francisco Bay Area or Jacksonville Metro location. The work is hands‑on in code, in waveforms, in synthesis reports, and in code review. If you need a mature RTL organization with established style guides, a senior RTL lead above you, and a deep pile of inherited IP, this is not the right fit. If you have wanted to be the engineer who establishes those things, you are in the right place.

Why Snowcap

Snowcap Compute is building the world's first commercial superconducting digital computer. Our chips operate at 4.5 Kelvin on Josephson junction‑based PCL logic, consuming a fraction of the power of any CMOS system. We are not improving the existing paradigm — we are replacing it.

We are a technically elite, small team at the intersection of quantum physics, cryogenic engineering, and advanced semiconductor manufacturing. Every person on this team has a direct line of sight to the product. The work you do here will be visible, consequential, and unprecedented.

This is a founding RTL seat. The coding standards, structural conventions, and ownership culture you set become the baseline every future RTL engineer at Snowcap builds on — and the blocks you author go straight into the first commercial superconducting digital chip.

Compensation

Full medical, dental, and vision 401(k) Relocation assistance available for candidates outside the area.

Base salary range is shown in USD, posted in good faith and in compliance with California pay transparency law (SB 1162). The range spans the L1 (new grad) entry floor through the senior individual‑contributor band — the offer Snowcap reasonably expects to make depends on the level of the seat being filled, plus experience, skills, and location. Range is exclusive of equity, bonus, and benefits. Range reflects the San Francisco Bay Area market; offers for the same role based in Jacksonville Metro, FL are typically 15–25% lower in line with local market norms.

Based in the San Francisco Bay Area or Jacksonville Metro, FL On‑Site.