Digital Sign-off Engineer

Snowcap Compute Inc.; San Francisco (CA); On-site; USD 130,000 - 230,000; Full time

Benefits offered by this job

Relocation assistance

On-site work in SF Bay Area

Job summary

Snowcap Compute Inc. is hiring a senior sign-off engineer to own the final verification of layouts, parasitic extraction, and timing across corners. You will drive DRC/LVS/ERC checks, power integrity, and antenna reviews, ensuring only clean tape-outs proceed.

Collaborate with RTL, physics, and fab teams. This on-site role is based in the SF Bay Area or Jacksonville Metro. You will shape the sign-off methodology, develop constraint scripts from scratch, and craft evidence packages for management

Qualifications

• Deep, production-level expertise with sign-off EDA tools
• Track record closing tape-out on production silicon as the sign-off engineer
• Strong post-layout STA skills with multi‑mode multi‑corner
• Working fluency with foundry rule decks and DRC waivers
• Sign-off of power integrity, IR drop, electromigration

Responsibilities

• Own the final physical and electrical verification of completed layouts against all design requirements
• Drive parasitic extraction and post-layout timing analysis across corners
• Execute DRC, LVS, ERC, and antenna checks against foundry rules
• Lead power integrity, IR drop, and electromigration sign-off analysis
• Own the sign-off checklist and gating decisions for tape-out
• Communicate sign-off status and risk to architects, RTL, implementation, and physics teams
• Author and maintain sign-off methodology, scripts, and constraint files

Skills

Sign-off tools

Tape-out ownership

Post-layout STA

Power integrity

Waiver documentation

Tools

Calibre

PrimeTime

Voltus

StarRC

Job description

About the Role

The chip program ends at sign-off, and sign-off is the last technical line of defense before a wafer is committed. The implementation team produces a design; this role decides whether that design is actually ready for fab. At Snowcap that decision is harder than at a CMOS shop — the PDK is non-standard, the rule decks are younger, and the extraction and timing assumptions that work at 7 nm CMOS do not transfer.
You will own the full sign-off flow: parasitic extraction, post-layout STA across corners, DRC, LVS, ERC, antenna, power integrity, EM, and the sign-off checklist that gates tape-out. You will work directly with the Implementation Engineer, RTL design, and the physics and fab teams in a flat, matrixed organization. You will be the engineer with the authority — and the obligation — to say "not yet" on a tape-out when the data does not support it, and to say "yes, this is the right waiver" when it does.
In twelve months, the sign-off methodology and checklists you stand up should be the artifact every tape-out decision at Snowcap runs through. The waiver discipline, the corner coverage, and the risk communication you establish become the standard every future sign-off engineer here inherits.

What You'll Own

• Own the final physical and electrical verification of completed layouts against the full set of design requirements — every check, every corner, every signed-off.


• Drive parasitic extraction and post-layout static timing analysis — set up the corners, interpret the results, and translate timing reports into actionable feedback for the implementation team.


• Execute and close DRC, LVS, ERC, and antenna checks against the foundry rule decks — including the judgment calls on what to fix versus what to waive.


• Drive power integrity, IR drop, and electromigration analysis appropriate to a superconducting current distribution that does not behave like CMOS.


• Own the sign-off checklist and the gating decision for tape-out — produce the evidence package, defend it under review, and be the engineer whose name is on "ready for fab".


• Communicate sign-off status and risk to the broader chip team in terms that architects, RTL, implementation, and physics can all act on.


• Author and maintain the sign-off methodology, scripts, and constraint files at Snowcap — including STA constraint development from scratch where the design has no inherited SDC.


• Partner with implementation on ECO planning when a sign-off finding requires a real fix late in the cycle.

What We Need to See

• Deep, production-level expertise with sign-off EDA tools — Calibre, Pegasus, StarRC, PrimeTime, Voltus, or equivalent — on chips that taped out and ran.


• Track record closing tape-out on production silicon as the sign-off engineer of record, not as an adjacent contributor.


• Strong post-layout STA skills: multi-mode multi-corner, constraint development from scratch, and the judgment to know which violations are real and which are constraint problems.


• Working fluency with foundry rule decks and the discipline around DRC waivers — when a waiver is legitimate, when it is hiding a real problem, and how to document either way.


• Solid working knowledge of power integrity, IR drop, and electromigration sign-off, and the interdependency between implementation choices upstream and sign-off outcomes downstream.


• Methodical, detail-oriented work style — sign-off rewards rigor, and the cost of a missed item is a tape-out, not a patch.

Ways to Stand Out

• Sign-off experience on a full-custom or semi-custom chip — anywhere the standard-cell sign-off flow had to be extended or partially re-derived. Significant differentiator.


• Experience working with non-CMOS or research-grade PDKs — NbTiN, NbN, or any node where the rule decks were not yet production-hardened and the methodology had to be built around it.


• Background at IBM Research, Intel custom logic, advanced ASIC houses, or comparable groups where sign-off carried real authority on tape-out decisions.


• Custom cell modeling experience — Nanotime or equivalent — including liberty model development for cells that did not come from a foundry library.


• Track record building sign-off flows and STA environments from scratch — constraint files, scripts, methodology — not just inheriting them.


• ECO planning and implementation experience at the late stage, where the cost of a missed sign-off finding becomes another spin.


• Familiarity with superconducting digital logic — PCL, SFQ, AQFP, RSFQ, or related — at any level. We do not require it; we will weight it heavily when we find it.

The Environment

Snowcap is a small, technically elite team running sign-off on a PDK that does not have decades of accumulated rule deck history behind it. The waivers, the corner sets, the methodology documents — they are not sitting in a wiki you can inherit. You will write them, and the next sign-off engineer to join builds on what you established.
We are a flat, matrixed organization. You will work daily with implementation, RTL design, design verification, and the fab and physics teams — directly, without layers. When a sign-off finding might gate a tape-out and the question is whether it is a real risk or a waiver, that conversation happens in the room that day, with the people who can act on it.
This role is on-site at our San Francisco Bay Area or Jacksonville Metro location. The work is hands-on at the sign-off tools, in extraction databases, in timing reports, and in rule deck triage. If you need a mature sign-off organization with established checklists, inherited constraint sets, and a methodology team standing behind you, this is not the right fit. If you have wanted to be the engineer whose checklist becomes the organizational standard, you are in the right place.

Why Snowcap

Snowcap Compute is building the world's first commercial superconducting digital computer. Our chips operate at 4.5 Kelvin on Josephson junction-based PCL logic, consuming a fraction of the power of any CMOS system. We are not improving the existing paradigm — we are replacing it.
We are a technically elite, small team at the intersection of quantum physics, cryogenic engineering, and advanced semiconductor manufacturing. Every person on this team has a direct line of sight to the product. The work you do here will be visible, consequential, and unprecedented.
This is the founding sign-off seat. The checklist, the methodology, and the waiver discipline you set become the gate every Snowcap tape-out runs through — and your name will be on the first commercial superconducting digital chip that goes to fab.

Compensation

Full medical, dental, and vision · 401(k) · Relocation assistance available for candidates outside the area.
Base salary range is shown in USD, posted in good faith and in compliance with California pay transparency law (SB 1162). The range spans the L2 (<3 yrs experience) entry floor through the senior individual-contributor band — the offer Snowcap reasonably expects to make depends on the level of the seat being filled, plus experience, skills, and location. Range is exclusive of equity, bonus, and benefits. Range reflects the San Francisco Bay Area market; offers for the same role based in Jacksonville Metro, FL are typically 15–25% lower in line with local market norms.
Based in the San Francisco Bay Area or Jacksonville Metro, FL · On-Site.