RTL Design Engineer

Acceler8 Talent; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent is seeking an experienced RTL Design Engineer (Staff/Principal) in Palo Alto, CA to own RTL development for a next-gen AI accelerator.

You will drive digital design, microarchitecture, verification, and tapeout readiness across ASIC/SoC blocks, collaborating with verification and physical design teams to meet stringent PPA targets.

Qualifications

• Must have extensive experience in digital hardware design with hands-on RTL development in ASIC/SoC.
• Strong proficiency in Verilog and/or SystemVerilog.
• Proven ability to develop complex RTL from architecture to implementation.
• Deep understanding of digital microarchitecture: datapaths, state machines, control logic.
• Knowledge of power, performance, and area optimization and its impact on RTL.
• Experience debugging complex RTL issues and timing challenges.
• Demonstrated collaboration with verification, microarchitecture, and physical design teams.
• Staff-to-Principal level technical judgment with hands-on RTL focus.

Responsibilities

• Translate architectural specs into detailed RTL and microarchitecture.
• Design and optimize datapaths, control logic, and interfaces.
• Balance throughput, latency, power, area, and timing trade-offs.
• Own RTL development, debugging, and integration for ASIC/SoC sections.
• Collaborate with verification to define functionality and debug corner cases.
• Work with physical design to analyze synthesis results and timing feedback.
• Drive design improvements based on timing and power targets.
• Own design blocks through tapeout readiness and documentation.

Skills

Digital hardware design

Verilog/SystemVerilog

RTL development

Digital microarchitecture

PPA optimization

RTL debugging

Cross-team collaboration

Hands-on RTL

Job description

RTL Design Engineer

Level:Staff / Principal

Palo Alto, CA

About the Role

An early-stage, venture-backed AI semiconductor startup is seeking an experienced RTL Design Engineer to help develop a next-generation chip purpose-built for large language model (LLM) inference.

The company is developing a specialized AI accelerator alongside its supporting software stack, with a focus on delivering efficient, high-performance inference.

This is a hands-on engineering role offering significant ownership across digital design, microarchitecture, verification, and physical implementation. You'll play a key role in bringing the company's first generation of silicon from architectural concepts through implementation and tapeout.

Key Responsibilities

• Translate high-level architectural specifications into detailed block-level microarchitecture and synthesizable RTL.
• Design, implement, and optimize complex datapaths, control logic, and inter-block interfaces.
• Make architectural and implementation trade-offs involving throughput, latency, power, area, and timing.
• Own RTL development, debugging, and integration for significant portions of the ASIC/SoC design.
• Collaborate with verification engineers to define expected functionality, debug failures, and resolve complex corner cases.
• Work closely with physical design teams to analyze synthesis results, timing constraints, and implementation feedback.
• Drive design improvements based on timing, power, and area requirements.
• Take ownership of assigned design blocks through integration, verification closure, and tapeout readiness.
• Document key design decisions, implementation risks, and technical trade-offs.

Required Qualifications

• Extensive experience in digital hardware design, with significant hands-on ownership of ASIC or SoC RTL development.
• Strong proficiency in Verilog and/or SystemVerilog.
• Proven ability to develop complex RTL from architectural specifications through implementation.
• Deep understanding of digital microarchitecture, including datapaths, state machines, control logic, concurrency, and cycle-level behavior.
• Strong knowledge of power, performance, and area (PPA) optimization and how RTL design choices influence physical implementation.
• Experience debugging complex RTL issues and resolving functional or timing-related challenges.
• Demonstrated collaboration with verification, microarchitecture, and physical design teams.
• Staff-to-Principal-level technical judgment, combined with a willingness to remain highly hands-on in RTL design and debugging.

Preferred Qualifications

• Experience designing AI accelerators, inference ASICs, GPUs, or other high-performance compute silicon.
• Familiarity with LLM inference workloads and specialized compute architectures.
• Experience with synthesis, static timing analysis, and physical design feedback.
• Previous involvement in successful ASIC/SoC tapeouts.
• Background working on first-generation silicon or early-stage hardware development.
• Experience collaborating across architecture, design verification, and physical implementation.

Why Join?

• Opportunity to help develop a purpose-built LLM inference accelerator from the ground up.
• Significant ownership of RTL and microarchitecture for first-generation silicon.
• Work directly with a highly technical founding engineering team.
• Influence key architectural decisions, design methodologies, and implementation strategies.
• Hands-on engineering environment with broad technical exposure and minimal organizational layers.
• Opportunity to make a meaningful impact on the development of next-generation AI computing hardware.

Hiring Process

The interview process typically consists of two to three conversations, including technical discussions covering previous projects, RTL design experience, and engineering problem-solving.

Additional details about the team, architecture, and technology roadmap will be shared under NDA as the process progresses.