RFSoC DSP FPGA Firmware Engineer — High-Throughput DSP

Xenon Innovations, Inc.; Fairfax (VA); On-site; USD 140,000 - 245,000; Full time

Job summary

Xenon Innovations, Inc. seeks an experienced FPGA/DSP engineer to design high-throughput datapaths for RFSoC-class devices. You will partition architectures, choose precision, and optimize latency with DSP and hardware teams.

You will develop synthesizable VHDL, build testbenches, verify against models, and manage timing closure and board bring-up with the team. This is a design-focused role.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related.
• 5+ years of FPGA development with substantive DSP content.
• Fluency in fixed-point arithmetic and its practical consequences.
• Hands-on experience with Xilinx/AMD tooling (Vivado, Vitis) or equivalent.
• Demonstrated ownership of timing closure on a nontrivial design.

Responsibilities

• Write synthesizable VHDL for high-throughput streaming DSP datapaths.
• Implement digital down/up conversion, polyphase channelizers, FIR and CIC filter chains, NCOs, and demodulation logic.
• Design and integrate AXI-Stream and AXI-Lite interfaces, DMA paths, and control/status register maps.
• Partition designs across programmable logic and processing system on SoC targets.
• Build and maintain self-checking testbenches with stimulus from DSP models.
• Perform bit-accurate comparisons against golden models and diagnose discrepancies.
• Maintain regression coverage as designs evolve across baselines.
• Own timing closure, floorplanning, and clock-domain crossing strategy.
• Track resource, power, and thermal budgets and flag risks early.
• Bring up new board designs alongside hardware team and debug in-system.

Skills

FPGA DSP experience

Fixed-point arithmetic

Timing closure ownership

Education

BS in Electrical Engineering / Computer Engineering or related

Tools

Xilinx Vivado/Vitis

Job description

Xenon Innovations, Inc. seeks an experienced FPGA/DSP engineer to design high-throughput datapaths for RFSoC-class devices. You will partition architectures, choose precision, and optimize latency with DSP and hardware teams.

You will develop synthesizable VHDL, build testbenches, verify against models, and manage timing closure and board bring-up with the team. This is a design-focused role.