RFIC Design Intern

Dormont Manufacturing Co; United States; On-site; USD 30,000 - 40,000; Full time

Benefits offered by this job

Paid internship

Opportunity for growth

Collaborative team environment

Job summary

Dormont Manufacturing Co is seeking a motivated RFIC Design Engineer Intern to support the development and simulation of RF integrated circuits. This internship offers hands-on experience and the chance to work closely with experienced engineers on developing new hardware innovations.

The ideal candidate will pursue a M.S. or Ph.D. in Electrical Engineering and have a solid background in RFIC design. Full-time or part-time applicants for Fall 2026 are encouraged to apply.

Qualifications

• 2+ years of RFIC design experience preferred.
• Strong background in RF state-of-the-art CMOS, SOI, or SiGe technologies.
• Experience with RFIC layout and post-layout simulation.

Responsibilities

• Assist with the design and simulation of RF/analog front-end circuit blocks.
• Perform circuit RF simulations including S-parameters and noise figure.
• Support layout reviews and parasitic extraction.

Skills

RFIC design experience

Proficient in Cadence Virtuoso

Experience with Python or MATLAB

Strong communication skills

Education

Currently pursuing M.S. or Ph.D. in Electrical Engineering

Tools

Cadence Virtuoso

Spectre RF

ADS

Job description

We are seeking a motivated RFIC Design Engineer Intern to support the development, simulation, and validation of RF integrated circuits for next-generation wireless and satellite communications applications. This internship is ideal for a student with strong fundamentals in analog/RF circuit design who wants hands‑on experience working with experienced RFIC engineers on real product development and help push new hardware innovations forward.

Responsibilities

As an RFIC Design Engineer Intern, you will:

• Assist with the design and simulation of RF/analog front‑end circuit blocks such as LNAs, mixers, oscillators, PLLs, PAs, VGAs, switches, etc.
• Perform circuit RF simulations including S‑parameters, noise figure, gain, linearity, stability, power consumption, etc.
• Support layout reviews, parasitic extraction, and post‑layout simulations.
• Assist in the analysis of 2.5D and 3D EM circuit models and simulation outcomes.
• Work across a cross‑functional collaborative team of bright RF engineers.
• Prepare technical documents and reports, and participate in design reviews and brainstorming sessions.

We are considering full‑time/ part‑time applicants for Fall 2026.

The ideal candidate will have strong technical competency, curiosity, and the ability to take the lead and ownership of a well‑defined project. They should also be excited to adapt, learn quickly, and grow in a fast‑paced startup environment.

Requirements

• Currently pursuing a M.S., or Ph.D. in Electrical Engineering with 2+ years of RFIC design experience.
• Strong background in RF state‑of‑the‑art CMOS, SOI, or SiGe technologies.
• Proficient in RFIC design and characterization tools such as Cadence Virtuoso, Spectre RF, ADS, or similar.
• Deep understanding of system specifications and capable of translating system requirements into circuit requirements at IC level.
• Experience with RFIC layout and post‑layout simulation.
• Experience with Python, MATLAB, or scripting for data analysis and automation.
• Prior research, or tapeout experience in RF/analog IC design.
• Comfortable working and solving problems independently as well as collaboratively within a team.
• Strong written and oral communication skills in English and comfortable explaining technical concepts to the rest of the team.

Benefits

• Paid, full‑time, onsite internship at our Bay Area, CA location with competitive salary.
• Opportunity to work with a collaborative and ambitious team developing disruptive products.
• Opportunities for growth, leadership, and project ownership in a dynamic startup environment.