RFIC Design Intern

Sky Gig

San Jose (CA)

Presencial

USD 52 000 - 70 000

Tempo integral

14 dias+

Uma candidatura completa num minuto

Currículo e carta de apresentação personalizados, prontos a enviar.

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Vantagens oferecidas por esta oferta de emprego

Paid internship
Opportunities for growth
Collaborative team environment

Resumo da oferta

Sky Gig is seeking an RFIC Design Engineer Intern in San Jose, CA to support the development of RF integrated circuits for next-generation wireless communications. The internship is ideal for students in Electrical Engineering with strong fundamentals looking for hands-on experience.

Candidates should have at least 2 years of RFIC design experience and proficiency in tools like Cadence Virtuoso and ADS. This full-time, onsite internship offers competitive remuneration and an opportunity to work in a dynamic startup environment.

Qualificações

  • Pursuing a M.S. or Ph.D. with 2+ years of RFIC design experience.
  • Proficient in RFIC design and characterization tools.
  • Experience with Python, MATLAB for data analysis.

Responsabilidades

  • Assist with design and simulation of RF/analog circuit blocks.
  • Perform RF simulations including S-parameters, noise figure.
  • Support layout reviews and analysis of EM circuit models.

Conhecimentos

Analog/RF circuit design
RF state-of-the-art CMOS technology
Cadence Virtuoso
System specifications understanding
Python scripting

Formação académica

M.S. or Ph.D. in Electrical Engineering

Ferramentas

Spectre RF
ADS

Descrição da oferta de emprego

We are seeking a motivated RFIC Design Engineer Intern to support the development, simulation, and validation of RF integrated circuits for next-generation wireless and satellite communications applications. This internship is ideal for a student with strong fundamentals in analog/RF circuit design who wants hands‑on experience working with experienced RFIC engineers on real product development and help push new hardware innovations forward.

We are considering full-time/ part-time applicants for Fall 2026.

The ideal candidate will have strong technical competency, curiosity, and the ability to take the lead and ownership of a well-defined project. They should also be excited to adapt, learn quickly, and grow in a fast‑paced startup environment.

Responsibilities
  • Assist with the design and simulation of RF/analog front‑end circuit blocks such as LNAs, mixers, oscillators, PLLs, PAs, VGAs, switches, etc.
  • Perform circuit RF simulations including S‑parameters, noise figure, gain, linearity, stability, power consumption, etc.
  • Support layout reviews, parasitic extraction, and post‑layout simulations.
  • Assist in the analysis of 2.5D and 3D EM circuit models and simulation outcomes.
  • Work across a cross‑functional collaborative team of bright RF engineers.
  • Prepare technical documents and reports, and participate in design reviews and brainstorming sessions.
Qualifications
  • Currently pursuing a M.S., or Ph.D. in Electrical Engineering with 2+ years of RFIC design experience.
  • Strong background in RF state‑of‑the‑art CMOS, SOI, or SiGe technologies
  • Proficient in RFIC design and characterization tools such as Cadence Virtuoso, Spectre RF, ADS, or similar.
  • Deep understanding of system specifications and capable of translating system requirements into circuit requirements at IC level.
  • Experience with RFIC layout and post‑layout simulation.
  • Experience with Python, MATLAB, or scripting for data analysis and automation.
  • Prior research, or tapeout experience in RF/analog IC design.
  • Comfortable working and solving problems independently as well as collaboratively within a team.
  • Strong written and oral communication skills in English and comfortable explaining technical concepts to the rest of the team.
Benefits
  • Paid, full‑time, onsite internship at our Bay Area, CA location with competitive salary
  • Opportunity to work with a collaborative and ambitious team developing disruptive products.
  • Opportunities for growth, leadership, and project ownership in a dynamic startup environment.
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