Remote CPU Architect: Vector, Matrix AI Compute

Tenstorrent

Northern (KY)

Hybrid

USD 100,000 - 500,000

Full time

9 days ago

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Job summary

Tenstorrent in the United States is seeking an experienced CPU Architect/Micro-Architect to lead the design of vector (RVV), floating point, and matrix extensions for high-performance RISC-V compute engines.

You will shape architecture and micro-architecture of compute units and subsystems, collaborate with software teams, silicon designers, and IP partners to optimize performance, power, and area for HPC/AI workloads. This role is remote, based out of North America.

Qualifications

  • 5+ years of experience in CPU design for HPC and AI acceleration.
  • Experience designing hardware for matrix FP computation, AI accelerators, vector processing, tensor engines, or ML workloads.
  • Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and CPU-accelerator interactions.
  • Experience defining architectural specifications and leading cross-functional teams from concept to silicon.
  • Experience with RTL development on cutting-edge AI frontier models.

Responsibilities

  • Drive architecture and micro-architecture of compute execution units and subsystems for HPC/AI workloads.
  • Translate workload requirements into scalable CPU architectures optimizing performance, power, and area.
  • Collaborate with software, silicon designers, and IP partners across hardware and software boundaries.
  • Define next-generation compute architectures for open RISC-V CPUs and AI infrastructure.

Skills

CPU architecture
AI acceleration
matrix math
floating point
heterogeneous compute systems
architectural decisions
cross-functional leadership

Job description

Tenstorrent in the United States is seeking an experienced CPU Architect/Micro-Architect to lead the design of vector (RVV), floating point, and matrix extensions for high-performance RISC-V compute engines.

You will shape architecture and micro-architecture of compute units and subsystems, collaborate with software teams, silicon designers, and IP partners to optimize performance, power, and area for HPC/AI workloads. This role is remote, based out of North America.

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