R&D Engineer

KB Search Team, LLC; United States; Hybrid; USD 100,000 - 130,000; Full time

Job summary

KB Search Team, LLC is seeking a full-time R&D Engineer to join the R&D Engineering team. The role involves design, simulation, prototyping, and testing of wireless communication and sensing projects, with a hybrid schedule requiring three onsite days weekly (Mon, Wed, Thu).

The successful candidate will work on HDL testbenches, FPGA design, and verification, using Xilinx FPGAs and Vivado, with Python or TCL scripting to automate tests and collect code coverage data.

Qualifications

• Bachelor in Electrical Engineering, Computer Science, or related field with 4 years FPGA design/testing experience OR 2 years with MS.
• Proven experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Experience with TCL or Python.

Responsibilities

• Architect testbenches for full-system HDL simulations.
• Maintain and improve existing HDL testing infrastructure.
• Automate certain testing using scripts.
• Collect, maintain, and use code coverage data from test suites.
• Design and code HDL blocks.
• Hardware verification and troubleshooting; familiarity with logic analyzers.

Skills

FPGA design

HDL design & verification

Python scripting

TCL scripting

Clock-domain design

Education

Bachelor of Science in Electrical Engineering or Computer Science

MS degree in Electrical Engineering

Tools

Xilinx Vivado IDE

Xilinx FPGAs

Job description

THE OPPORTUNITY

Our client is seeking a full-time R&D Engineer reporting to the Director of R&D Engineering on the R&D Engineering team. The successful individual in this role will participate in the design, simulation, prototyping, and testing of wireless communication and sensing projects and products. This position is on a hybrid schedule, a minimum of 3 days onsite per week is expected. On-site days are: Mondays, Wednesdays, and Thursdays.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

• Architect testbenches for full-system HDL simulations.
• Maintain and improve existing HDL testing infrastructure.
• Automate certain testing using scripts.
• Collect, maintain, and use code coverage data from test suites.
• Design and code HDL blocks.
• Hardware verification and troubleshooting; familiarity with logic analyzers.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant field plus 4 years of demonstrated experience in FPGA design and testing/verification OR 2 years of FPGA experience in design and testing/verification with an MS or advanced degree.
• Proven experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Experience with tcl or python.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• Master of Science degree in Electrical Engineering (MSEE).
• Demonstrated experience with fixed point binary arithmetic, and digital signal processing designs.
• Basic MATLAB skill.
• Experience with communication systems on FPGA or ASIC designs.

COMPENSATION

The pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate's experience and qualifications.

CA Pay Range

$100,000---$130,000 USD