R&D Engineer

Talent With Heart; Los Angeles (CA); Hybrid; USD 100,000 - 130,000; Full time

Job summary

Talent With Heart in Los Angeles is seeking a full-time R&D Engineer to join the R&D Engineering team. You will participate in design, simulation, prototyping, and testing of wireless communication and sensing projects, reporting to the Director of R&D Engineering.

This hybrid role requires at least a BS in EE/CS with FPGA design and testing experience, familiarity with Xilinx FPGAs, Vivado, HDL, and scripting (TCL or Python). On-site days are Mon, Wed, Thu.

Qualifications

• Bachelor of Science in Electrical Engineering, Computer Science, or related field with 4 years FPGA design/testing experience, or MS with 2 years experience.
• Proven experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Experience with TCL or Python.

Responsibilities

• Architect testbenches for full-system HDL simulations.
• Maintain and improve existing HDL testing infrastructure.
• Automate certain testing using scripts.
• Collect, maintain, and use code coverage data from test suites.
• Design and code HDL blocks.
• Hardware verification and troubleshooting; familiarity with logic analyzers.

Skills

FPGA design

HDL testing

Python / TCL

Clock-domain design

HDL testbenches

Education

Bachelor of Science in Electrical Engineering or Computer Science

MS or advanced degree in relevant field

Tools

Vivado IDE

Xilinx FPGAs/SoCs

Job description

THE OPPORTUNITY

Our client is seeking a full-time R&D Engineer reporting to the Director of R&D Engineering on the R&D Engineering team. The successful individual in this role will participate in the design, simulation, prototyping, and testing of wireless communication and sensing projects and products. This position is on a hybrid schedule, a minimum of 3 days onsite per week is expected. On-site days are: Mondays, Wednesdays, and Thursdays.

ROLE AND RESPONSIBILITIES

• Architect testbenches for full-system HDL simulations.
• Maintain and improve existing HDL testing infrastructure.
• Automate certain testing using scripts.
• Collect, maintain, and use code coverage data from test suites.
• Design and code HDL blocks.
• Hardware verification and troubleshooting; familiarity with logic analyzers.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant field plus 4 years of demonstrated experience in FPGA design and testing/verification OR 2 years of FPGA experience in design and testing/verification with an MS or advanced degree.
• Proven experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Experience with tcl or python.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• Master of Science degree in Electrical Engineering (MSEE).
• Demonstrated experience with fixed point binary arithmetic, and digital signal processing designs.
• Basic MATLAB skill.
• Experience with communication systems on FPGA or ASIC designs.

COMPENSATION

The pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate's experience and qualifications.

CA Pay Range

• $100,000---$130,000 USD