Programmable Logic and ASIC Design Center of Excellence Lead

Anysilicon; Orlando, Northern (FL, KY); Hybrid; USD 190,000 - 230,000; Full time

Job summary

Lockheed Martin seeks a seasoned Programmable Logic and ASIC Center of Excellence Lead for the MFC organization. You will define the CoE charter, oversee architecture, verification, and post-silicon activities while driving automation and cross-program standards.

You will mentor engineers, manage resources, and coordinate IRAD efforts, reporting to senior MFC leadership. This senior role demands deep defense-grade PL/ASIC expertise.

Qualifications

• Bachelor’s degree in Electrical Engineering; Master’s preferred.
• 20+ years hands-on PL and/or ASIC design in defense programs.
• 5+ years in Lockheed Martin's MFC area.
• Demonstrated success leading a CoE or similar group.
• Excellent written and verbal communication skills.

Responsibilities

• Define and maintain the CoE charter, roadmap, and multi-year plan.
• Chair CoE meetings and quarterly steering reviews with VP-level goals.
• Lead design tools and improve automation flows for PL/ASIC.
• Set digital design/verification standards across MFC programs.
• Oversee PLD/ASIC implementation, architecture and verification.
• Manage post-silicon bring-up, validation and debug.
• Create reusable assets and coordinate IRAD projects for reuse.
• Design and deliver CoE training and mentor engineers.
• Disseminate CoE communications and maintain PLM docs.
• Liaise with senior leadership to secure resources and recruit.
• Contribute technically to MFC programs as IC.

Education

Bachelor’s degree in Electrical Engineering

Master’s degree preferred

Tools

LM design tools

MBSE tooling

CI/CD tooling

Job description

Programmable Logic and ASIC Design Center of Excellence Lead

Job Description:

The Programmable Logic & ASIC Center of Excellence (CoE) Lead for the Missiles & Fire Control (MFC) organization at Lockheed Martin is responsible for overseeing hardware development for programmable logic devices and custom ASICs. This role involves setting strategic direction, defining the CoE charter, and ensuring alignment with senior leadership while driving automation and continuous improvement in design processes.

Responsibilities:

• Define and maintain the CoE charter, roadmap, and multi-year improvement plan.
• Chair CoE meetings and host quarterly steering committee reviews to align deliverables with VP-level goals.
• Act as the authority for PL/ASIC design tools and lead continuous improvement of design automation flows.
• Establish and enforce common digital design and verification standards across MFC programs.
• Oversee PLD and ASIC implementation activities, including architecture definition and functional verification.
• Manage post-silicon bring-up, validation, and debug activities for successful system integration.
• Drive the creation of reusable assets and coordinate IRAD projects for PL/ASIC reuse.
• Design and deliver CoE training curriculum and mentor junior engineers.
• Consolidate and disseminate CoE communications and maintain documentation in PLM tools.
• Liaise with senior leadership to secure resources and support recruitment efforts.
• Contribute technical expertise to MFC programs as an individual contributor.

Qualifications:

• Bachelor’s degree in Electrical Engineering or related field; Master’s degree preferred.
• Minimum 20 years of hands-on PL and/or ASIC design experience in defense-grade programs.
• At least 5 years of experience within Lockheed Martin's MFC business area.
• Demonstrated success leading a CoE or comparable technical group.
• Deep knowledge of LM MFC PL and/or ASIC design tools and processes.
• Proven record of building training programs for electrical engineers.
• Excellent written and verbal communication skills.

Skills:

• Current or emeritus Group Technical Staff (GTS) member or Lockheed Martin Fellow.
• Active participation in internal technical focus groups.
• Exposure to AI-assisted layout tools and model-based systems engineering (MBSE).
• Proficiency with HDL languages (SystemVerilog or VHDL) and UVM-based verification.
• Experience with common-core digital standards and coding/verification templates.
• Familiarity with continuous integration pipelines and versioning for design tools.