Principal Test Engineer — Scan Insertion, ATPG & MBIST

American IT Systems; Santa Clarita (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Professionals with 8–12 years of experience in SOC test and validation are sought to lead scan insertion, ATPG, and MBIST related tasks. The role emphasizes hands-on experience with Tessent/Tessent Suite, Modus, and industry-standard EDA tools, including Synopsys and Cadence flows, within an Intel-ecosystem context.

Strong skills in coverage analysis, test point insertion, and GLS validation for FC/SOC flows are highly valued.

Qualifications

• Experience with Tessent and Modus for stuck-at and transition (at-speed) fault models, including coverage analysis and test point insertion.
• Good hands-on experience with ATPG GLS(ZD +SDF) simulation debugs
• Working experience on SSN Pattern Retarget & FC/SOC GLS validation
• Experience of working in Intel environment

Responsibilities

• Perform scan insertion and ATPG validation for SOC.
• Collaborate on coverage analysis and test point insertion to improve test quality.

Skills

Scan insertion

ATPG Validation

SOC testing

Tessent

Modus

Stuck-at fault

Transition fault

Coverage analysis

Test point insertion

FC Compiler

Tetramax

VCS

Verdi

Spyglass

Cadence Xcelium

Intel environment

Tools

Mentor Tessent Scan

Tessent TestKompress

Synopsys FC Compiler

Tetramax

VCS

Verdi

Spyglass

Cadence Xcelium

Job description

Professionals with 8–12 years of experience in SOC test and validation are sought to lead scan insertion, ATPG, and MBIST related tasks. The role emphasizes hands-on experience with Tessent/Tessent Suite, Modus, and industry-standard EDA tools, including Synopsys and Cadence flows, within an Intel-ecosystem context.

Strong skills in coverage analysis, test point insertion, and GLS validation for FC/SOC flows are highly valued.