Principal Systems Engineer

Qreer.com; San Diego (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

An established industry player is seeking a Principal Systems Engineer to lead the architecture of complex EUV source systems. This role involves balancing requirements, overseeing system design, and ensuring optimal integration of subsystems. You will contribute to groundbreaking technology that enables the production of faster, energy-efficient microchips, impacting the future of consumer electronics. Join a dynamic team dedicated to innovation and excellence, where your expertise will drive the development of cutting-edge lithography machines. If you are passionate about engineering and want to make a significant impact in the semiconductor industry, this opportunity is for you.

Qualifications

• Expertise in system architecture and technical integration for complex systems.
• Strong background in mechanics and thermal design.

Responsibilities

• Oversee overall EUV source system architecture and technical integration.
• Prepare technical input for key program decisions and manage deliverables.

Skills

System Engineering

Technical Integration

Mechanical Design

Thermal Design

Gas and Vacuum Design

Education

Bachelor's Degree in Engineering

Master's Degree in Engineering

Job description

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Principal Systems Engineer, San Diego - CA

Location:

Job Category:

Recruitment/HR

Job Reference:

13747

Job Views:

49

Posted:

25.01.2025

Expiry Date:

11.03.2025

Job Description:

ASML brings together the most creative minds in science and technology to develop lithography machines that are key to producing faster, cheaper, energy-efficient microchips.

Introduction
ASML US, LP brings together the most creative minds in science and technology to develop lithography machines that are key to producing faster, cheaper, more energy-efficient microchips. We design, develop, integrate, market and service these advanced machines, which enable our customers - the world’s leading chipmakers - to reduce the size and increase the functionality of their microchips, which in turn leads to smaller, more powerful consumer electronics. Our headquarters are in Veldhoven, the Netherlands, and we have 18 office locations around the United States including main offices in Wilton, CT, Chandler, AZ, San Jose, CA and San Diego, CA.
This position requires access to controlled technology, as defined in the Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with applicants who are immediately eligible to access controlled technology.

Job Mission
The EUV source is a complex integrated system utilizing a high power CO2 laser to irradiate liquid tin droplets, creating a laser produced plasma (LPP). The plasma produces EUV light at 13.5nm wavelength, enabling leading edge lithography tools to print complex circuit patterns for the fabrication of integrated circuits. This technical innovation enables the continued scaling of device speed, power and density for every major semiconductor manufacturer. At ASML, system engineering (SE) translates the customer requirements for new products into a system design. During the design and integration process System Engineering guides Development & Engineering (D&E), guards the specifications and verifies the performance at system level at the end of the development process.

Responsibilities:

• Responsible for overall EUV source system architecture. Balances requirements against impact; manages cross-sectoral technical integration.
• Oversee system design with focus on mechanics, dynamics, system layout, thermal, gas and vacuum design.
• Deliverables: Feasibility Test Definitions, Product Feasibility Reports, product performance specifications and design specifications, system level alpha test definition and acceptance reports.
• Prepares technical input to key program decisions for review by senior executives. Manage system engineering deliverables to the product generation process such as identification of key technical risks, system performance projections and status of the overall architecture development.
• Responsible for optimal functional integration of subsystems into the whole product (guiding the product integration plan).
• Performs other duties as assigned.