Principal/Senior Staff/Staff CPU Design Engineer

SQL Pager LLC; San Francisco, California, Sunnyvale (CA, MO, CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

An innovative firm is seeking a Principal/Senior Staff ASIC Design Engineer to join their talented team in revolutionizing low latency systems. This role involves designing and optimizing complex SoCs using RISC-V architecture, where your expertise in RTL Logic Design and low-power techniques will be crucial. You will collaborate with cross-functional teams to ensure high performance and quality in mission-critical applications. If you are passionate about pushing the boundaries of technology and thrive in a fast-paced environment, this position offers an exciting opportunity to make a significant impact in the industry.

Benefits

Medical insurance

Vision insurance

Dental insurance

401(k)

Qualifications

• 10+ years as CPU Design Engineer for complex SoCs.
• Expert in RTL Logic Design and low-power design.

Responsibilities

• Participate in architecture definition and modeling for ASIC.
• Develop micro-architecture specification and verify designs.

Skills

RTL Logic Design

Low Power Design

Verilog/System Verilog

Scripting (Tcl, Python)

CPU Design Engineering

ASIC Design Phases

Education

BSEE/BSCE or equivalent

Master’s degree in science

Tools

Open-source design environments

Job description

Principal/Senior Staff/Staff ASIC Design Engineer (RISC-V)

Client Overview

Client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, Client is targeting best in class latency with order of magnitude improvements for years to come.

Low Latency has become the key enabler for the industry and other real-time applications, and the current industry’s state-of-the-art is just not up to the task. Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC to deliver unrivaled products to mission-critical and real-time applications.

This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellence. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality, and cost.

We’re changing the meaning of low latency and we want individuals ready to rise up to the challenge and take the industry by storm.

Job Responsibilities

1. We are seeking a dedicated CPU design engineer as part of ASIC for our mission using artificial intelligence computing architecture.
2. As CPU Design Engineer, you will be participating in architecture definition and modeling, verification test plan, and testbench architecture.
3. You will be responsible for developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals.
4. Collaborate with Algorithm and Verification teams to design various functional IPs in RISC-V based complex SoC.
5. Define a micro-architecture for the implementation and the usage of the functional block IP, possibly with externally sourced IPs.
6. Participate in SoC level integration and verifications.
7. Work with the Physical design team for the timing closure.

Required Skills

10+ years (Principal) / 7+ years (Senior Staff) / 5+ years (Staff) of general experience as a CPU Design Engineer for building complex SoCs.

• Experience in converting a module-level micro-architecture definition from given marketing requirements.
• Expert in RTL Logic Design, CDC, RDC, Scan insertion, Lint, LEC, and synthesis with timing constraints.
• Experience in low-power design with UPF.
• Proficient in scripting with Tcl, Python, and/or similar language.

At least gone through entire ASIC design phases from micro-architecture to post-silicon bringing-up and validation.

In-depth design knowledge in one or more of the following subjects:

• Instruction fetch and decode, branch prediction
• Instruction scheduling and register renaming
• Out-of-order execution
• Integer and Floating-point execution
• SIMD or Vector execution
• Load/Store execution, prefetching, memory ordering
• Virtualization, Hypervisor
• CPU Caches and Coherence
• MMU, Memory/DRAM Controller, Latency-hiding
• Inter-connect bus fabric, AMBA, CHI, NoC
• Priority based Programmable Interrupt Controller
• Debug and Trace
• Low Power Implementation
• Chip Security
• Cryptography

Nice to have

• Experience in working with open-source design environments and tools.
• Direct experience in RISC-V ISA specifications and the design compliances.
• FPGA Design Prototyping for pre-silicon design validation.
• Experience in ISO-26262 ASIL Requirements.

Education

BSEE/BSCE or equivalent. Master’s degree in science is preferred, but not required.

Featured benefits

• Medical insurance
• Vision insurance
• Dental insurance
• 401(k)