Principal RTL Engineer for Low-Power SoC & Pre-Tapeout

Ambiq Micro Inc; Austin (TX); On-site; USD 150,000 - 200,000; Full time

Job summary

Ambiq Micro Inc is seeking a Principal RTL Engineer to lead pre-tapeout quality for digital SOC modules. This hands-on role requires expertise in Verilog/SystemVerilog and SOC design technologies.

The ideal candidate will have at least 20 years of experience and a bachelor's degree in a relevant engineering field. Join a dynamic team committed to innovation and energy efficiency in Silicon design.

Located in Austin, TX, Ambiq offers an opportunity to make a significant impact in the semiconductor industry.

Qualifications

• 20 years of experience in SOC design.
• Deep understanding of customer needs and competitive landscape.
• Ability to estimate and lead implementations.

Responsibilities

• Own and be responsible for pre-tape out quality.
• Explore architecture and develop micro-architecture.
• RTL development for IPs and SOCs.

Skills

Verilog/SystemVerilog RTL development

SOC design technologies

Quality checks (LINT, CDC, RDC)

Collaboration with verification and FPGA teams

Education

Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering

Job description

Ambiq Micro Inc is seeking a Principal RTL Engineer to lead pre-tapeout quality for digital SOC modules. This hands-on role requires expertise in Verilog/SystemVerilog and SOC design technologies.

The ideal candidate will have at least 20 years of experience and a bachelor's degree in a relevant engineering field. Join a dynamic team committed to innovation and energy efficiency in Silicon design.

Located in Austin, TX, Ambiq offers an opportunity to make a significant impact in the semiconductor industry.