Principal RFIC Design Engineer - Chip Lead

Oso Semiconductor Inc.; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Oso Semiconductor Inc. in Mountain View, CA, is seeking a Principal RFIC Design Engineer – Chip Lead to own top-level integration of our next-generation multi-channel beamformer ICs.

You’ll drive chip architecture, floorplanning, block integration, RF/analog performance, physical implementation, package interfaces, and tapeout readiness across RF, analog, digital, layout, and test functions. This senior role requires leading execution from architecture to silicon bring-up, working directly with

Responsibilities

• Own top-level integration of multi-channel beamformer ICs.
• Drive chip architecture, floorplanning, block integration, and tapeout readiness across RF, analog, digital, layout, and test.
• Turn system requirements into manufacturable, testable products and drive execution from architecture through silicon bring-up.

Skills

RFIC design

Chip architecture

Floorplanning

Tapeout readiness

Layout coordination

Job description

We’re looking for a Principal RFIC Design Engineer - Chip Lead to own top-level integration of our next-generation multi-channel beamformer ICs. You’ll drive chip architecture, floorplanning, block integration, top-level RF/analog performance, physical implementation, package interfaces, and tapeout readiness across RF, analog, digital, layout, and test functions.

This is a senior technical leadership role for an experienced IC designer who can see the whole chip. You’ll work directly with the founding engineers and block owners to turn system requirements into a manufacturable, testable product and drive execution from architecture and floorplan through sign-off, silicon bring-up, and customer deployment.