Principal RFIC Design Engineer

Oso Semiconductor; Mountain View (CA); Hybrid; USD 150,000 - 190,000; Full time

Benefits offered by this job

Stock option grant

Unlimited PTO

Comprehensive health coverage

Job summary

Oso Semiconductor, located in Mountain View, California, is seeking a Principal RFIC Design Engineer to join their innovative team. In this role, you'll take ownership of designing mmWave front-end circuit blocks for our next-generation beamformer chips, collaborating closely with founding engineers.

The ideal candidate will have a strong background in RF/mmWave IC design, proficiency with Cadence EDA tools, and a passion for mentoring. This opportunity offers design autonomy within a fast-paced, cutting-edge environment, with significant career growth possibilities.

Qualifications

• MS + 5 years or PhD + 2 years in Electrical Engineering.
• Expertise in PA, LNA, phase shifters, VGAs, mixers at mmWave frequencies.
• Experience with full tapeout cycle.

Responsibilities

• Design mmWave front-end circuit blocks for beamformer chips.
• Perform schematic design, simulation, and layout.
• Support silicon bring-up and debugging of chips.

Skills

RF/mmWave IC design

Cadence EDA tools

Transistor-level design

EM simulation tools

Mentorship

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Virtuoso

Ansys HFSS

ADS Momentum

Job description

About Oso Semiconductor

Oso Semiconductor is an early‑stage fabless semiconductor company developing next‑generation mmWave beamforming technology. Founded by UC Berkeley PhDs, our proprietary RFIC architecture delivers 2–4x power reduction for phased array systems across satellite communication (SATCOM), 5G, and radar. We’ve raised Series A funding, secured our first defense and commercial customers, and are preparing to scale the team 3X.

The Role

We’re looking for a Principal RFIC Design Engineer to join the core design team. You’ll design, simulate, and validate mmWave front‑end circuit blocks for our next‑generation beamformer chips—including LNAs, PAs, phase shifters, VGAs, and complete transceiver signal chains.

This is a senior technical role with significant design ownership. You’ll work directly with the founding engineers, contribute to architecture decisions, and see your designs go from schematic to silicon to customer products.

Responsibilities

• Design mmWave front‑end circuit blocks (PAs, LNAs, phase shifters, VGAs, mixers) in advanced CMOS or RFSOI (SiGe and III‑V processes are a plus).
• Perform transistor‑level schematic design, simulation, and optimization using Cadence Virtuoso (Spectre, ADE).
• Conduct full‑custom IC layout or direct layout engineers, ensuring DRC/LVS‑clean designs at mmWave frequencies.
• Perform post‑layout extraction and EM simulation (Ansys HFSS, EMX, ADS Momentum) to validate performance through parasitics.
• Collaborate on chip‑level architecture and system partitioning for multi‑channel beamformer ICs.
• Support silicon bring‑up, bench characterization, and debugging of fabricated chips.
• Contribute to tapeout preparation, design reviews, and documentation.
• Mentor junior RFIC designers and contribute to a culture of technical excellence.

Required Qualifications

• MS + 5 years industry experience or PhD + 2 years industry experience in Electrical Engineering with a focus on RF/mmWave IC design.
• Demonstrated expertise in at least two of: PA, LNA, phase shifter, VGA, mixer, or frequency multiplier design at mmWave frequencies.
• Expert proficiency with Cadence EDA suite (Virtuoso, ADE, and Layout) and EM simulation tools (Ansys HFSS, EMX, or ADS Momentum).
• Experience with at least one full tapeout cycle: schematic to layout to fabrication to bring‑up to characterization.
• Strong understanding of mmWave transmission line theory, matching networks, and on‑chip passive design.
• Track record of published work or shipped products demonstrating circuit design excellence.

Preferred Qualifications

• Experience with phased array or multi‑channel beamformer IC design.
• Background in SATCOM, 5G NR FR2, or automotive radar mmWave applications.
• Experience in SOI nodes with high resistivity substrates.
• Familiar with system‑level RF specs: EVM, P1dB, noise figure, IP3, EIRP, and G/T.
• Experience in a startup or small‑team environment with high design ownership.
• Strong communication skills and ability to present design tradeoffs clearly.

Why Oso Semi?

• Design ownership: You own blocks from concept to silicon.
• Small team: Your voice matters in every architecture decision.
• Cutting‑edge process: Advanced nodes for mmWave—the hardest corner of IC design.
• Meaningful equity: Competitive stock option grant. Early engineers capture real value.
• UC Berkeley DNA: Founded by PhDs published in IEEE conferences and journals.
• First Principles Innovation: Multiple patents providing 2‑4x reductions in power.
• Established Traction: Signed multi‑year, high‑volume customer agreements in defense and commercial markets (SATCOM, radar, and 5G).

What We Offer

• Equity: Stock option grant with 4‑year vesting and 1‑year cliff.
• Medical, Dental & Vision: Comprehensive health coverage with employer‑sponsored medical, dental, and vision plans.
• Hybrid Schedule: Monday–Wednesday in office.
• Time Off: Unlimited PTO.
• 401(k): Employer‑matched retirement plan.
• Parental Leave: Equal parental leave for all parents.
• Team Culture: Regular team lunches, events, and celebrations.
• Life Insurance: Company‑paid life insurance.
• FSA & HSA: Flexible spending and health savings account options available.
• Commuter Benefits: Pre‑tax transit and parking benefits.

Oso Semiconductor is an equal opportunity employer. We consider all qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic.