Principal Product Engineer

Cadence Design Systems; San Jose (CA); On-site; USD 136,000 - 254,000; Full time

Job summary

A leading technology company is seeking a Product Engineer focused on ASIC design methodologies within a dynamic engagement environment. You will play a critical role in delivering customer solutions by leveraging your expertise and communication skills. Your responsibilities will include debugging, collaborating with teams, and contributing to product development and testing. Ideal candidates will have relevant industry experience and the ability to adapt to fast-paced challenges in digital implementation.

Benefits

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision plan options

Qualifications

• 5+ years of relevant industrial experience in digital implementation.
• Experience in design and EDA with emphasis on Cadence tools.
• Strong analysis skills to debug complex problems.

Responsibilities

• Providing first line BU support to AEs.
• Track and debug customer issues and work closely with R&D.
• Collaborate with account teams to deliver outstanding customer support.

Skills

Synthesis

PPA optimization

Debugging

Communication

Analysis

Automation skills

Education

MS in Electrical Engineering or ECE with focus on VLSI

Tools

Cadence tools

Genus

Innovus

Perl

Tcl

HDL – Verilog or System Verilog

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG) at Cadence. The Cadence DSG will offer you a dynamic environment in which you will work with R&D, Application Engineering (AE) team, Product Marketing (PM) team to influence the development of software tools for advanced chip design platforms.

As engagement focused PE, you will be focused on leveraging your acquire expertise and position within the business unit, to ensure the best outcomes for our customers. You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies from RTL to GDSII with a strong history of self-improvement and learning.

You will have proven hands-on experience with Synthesis and PPA optimization on more advanced nodes and will combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach. As an excellent communicator and competent presenter, with a healthy appreciation for continuous learning, you will be expected to ensure lessons are learnt from each engagement are shared more broadly between PE, AE, PM and R&D.

Since you will be joining a highly competent PE team with extensive PPA tuning and Layout experience, having experience of either RTL design and/or associated tool knowledge is preferrable but not essential. Coding skills, with Python and Tcl are also highly beneficial for this role, given future AI trends.

Job responsibilities:

• Using your acquired knowledge of Cadence Digital and Signoff products, provide first line BU support to AEs
• Track and debug customer issues and work closely with R&D on issue resolution
• Assist with flow development and testing in preparation for wider consumption by our field teams
• Collaborate with designated account teams to delivery excellent customer support
• Help with escalation of prioritised issues and identification of critical enhancements
• Sharing of knowledge

Preferred Qualifications:

• Requires a MS in Electrical Engineering or ECE with focus on VLSI with 5yrs or more years of relevant industrial experience
• Experience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes
• Prior Designer, Product Engineering or Application Engineering experience in digital implementation
• Understand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes
• Industry experience with EDA tools in the IC digital implementation flow, preferably on Genus and Innovus
• Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs
• Automation skills using Perl, Tcl and shell scripting essential
• Knowledge of HDL – Verilog or System Verilog is preferred
• Bonus to have logic design and/or timing closure skills
• Strong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D
• Proven track record and experience working in a fast-paced environment

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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