Principal Physical Design Engineer — Equity & High-Impact Chip

Delos Data Inc; United States; Remote; USD 180,000 - 260,000; Full time

Job summary

Delos Data Inc. seeks a Principal Physical Design Engineer to join as an early team member. You will own complex blocks from floorplan through signoff, driving timing, power integrity, and signoff challenges across the chip.

You will mentor peers, develop robust flows, and collaborate with RTL, verification, and packaging teams to meet aggressive performance targets in a fast-paced environment.

Qualifications

• 10+ years of ASIC or SoC physical design experience with multiple successful tapeouts.
• Strong expertise in floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification.
• Strong scripting and automation using Tcl, Python, Perl, or similar languages.
• Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools.

Responsibilities

• Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff.
• Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability.
• Develop and optimize power-grid implementations and support IR-drop and electromigration closure.
• Drive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation.
• Own difficult setup, hold, signal-integrity, congestion, and physical implementation problems.
• Lead timing closure across block boundaries and support top-level timing convergence.
• Perform and drive static timing analysis across multiple modes and corners.
• Support signal-integrity analysis and timing impact from crosstalk, variation, and physical effects.
• Drive physical signoff, including DRC, LVS, antenna, density, connectivity, and related physical verification requirements.
• Perform or support power integrity analysis, including static and dynamic IR drop and electromigration.
• Develop implementation strategies for high-performance and physically challenging portions of the design.
• Partner with RTL and architecture teams to identify implementation problems early and recommend architectural or logical changes where appropriate.
• Work closely with DFT, verification, package, SI/PI, and other engineering teams to resolve cross-functional design issues.
• Develop and improve physical design flows, scripts, automation, metrics, and methodologies.
• Evaluate implementation results and identify opportunities to improve PPA, runtime, convergence, and design quality.
• Provide technical guidance and mentorship to other physical design engineers.
• Participate in design reviews, methodology reviews, and tapeout readiness assessments.
• Serve as a technical escalation point for complex physical design and signoff issues.

Skills

Floorplanning & placement

Timing closure

Power integrity & IR drop

Scripting & automation

Debug RTL/Timing/Physical

Clock design & constraints

Leadership without management

Tools

Cadence tools

Synopsys tools

Job description

Delos Data Inc. seeks a Principal Physical Design Engineer to join as an early team member. You will own complex blocks from floorplan through signoff, driving timing, power integrity, and signoff challenges across the chip.

You will mentor peers, develop robust flows, and collaborate with RTL, verification, and packaging teams to meet aggressive performance targets in a fast-paced environment.