Principal Physical Design Engineer - Chiplet SoCs

Eliyan; United States; On-site; USD 180,000 - 300,000; Full time

Job summary

Eliyan is seeking a Principal Physical Design Engineer to lead the full ASIC physical design flow from RTL to GDSII. You will drive floorplanning integration, clocking architecture, and power planning for cutting-edge chiplet-based SoCs in a fast-paced startup environment.

You will oversee EM/IR analysis, PV signoff, and the development of scalable design flows to ensure high-quality, on-time tapeouts. Strong cross-functional collaboration and leadership are essential in this high-growth stage.

Qualifications

• Experience owning floorplanning, integration, clocking and power planning for complex SoCs from feasibility to tapeout.
• Expertise in architecture and package-driven hierarchy planning with lego-aligned boundaries and CTS methodologies.

Responsibilities

• Architectural and packaging driven floorplanning and integration to match system constraints.
• Define clocking architecture and CTS strategy to optimize power, skew, latency, and robustness.
• Lead EM/IR and PV signoff, identify hotspots, and reinforce grid with via optimization.

Skills

ASIC physical design

Floorplanning

Clocking & power planning

EM/IR analysis

Job description

Eliyan is seeking a Principal Physical Design Engineer to lead the full ASIC physical design flow from RTL to GDSII. You will drive floorplanning integration, clocking architecture, and power planning for cutting-edge chiplet-based SoCs in a fast-paced startup environment.

You will oversee EM/IR analysis, PV signoff, and the development of scalable design flows to ensure high-quality, on-time tapeouts. Strong cross-functional collaboration and leadership are essential in this high-growth stage.