Principal Mixed-Signal ASIC Architect - Photonics

Anysilicon; New York (NY); Presencial; USD 180.000 - 260.000; Jornada completa

Descripción de la vacante

Voyant Photonics is seeking a Principal Mixed-Signal ASIC Engineer to lead the development of custom ICs for silicon photonic chips. You will shape the ASIC strategy, drive tapeouts across 130 nm and below, and mentor a small team of designers in a cutting-edge robotics and AI data-center environment.

The role emphasizes low-noise TIAs, mixed-signal design, and collaboration with photonics, FPGA, and digital teams, with a fast track to delivering silicon within 9–12 months.

Formación

• 7+ years in analog and mixed-signal IC design
• Led multiple tapeouts from concept to production silicon
• Deep expertise in low-noise analog circuit design (TIAs)
• Knowledge of test plan development for analog ASICs at OSAT partners
• Strong mixed-signal design including ADCs, DACs, bias circuits, PM
• Experience with mature and advanced nodes and interfacing with digital design
• Ability to deliver working silicon within 9–12 months
• Excellent communication and collaboration skills

Responsabilidades

• Drive analog tapeouts from concept to production across 130 nm and below
• Design ultra-low-noise TIAs with pA/Hz noise performance
• Develop mixed-signal circuits (amplifiers, ADCs, DACs, PM) interfacing with photonic ICs
• Establish the ASIC development environment by selecting EDA tools and defining design flows
• Collaborate with photonics designers, systems engineers, and FPGA/digital teams
• Provide HDL and architectural input to external digital design partners
• Hire and mentor a small team of analog and digital IC designers

Conocimientos

Analog design

Mixed-signal design

Tapeouts

TIAs

Test plans

ADC/DAC design

Power management

Collaboration

Herramientas

EDA tools

Descripción del empleo

Voyant Photonics is seeking a Principal Mixed-Signal ASIC Engineer to lead the development of custom ICs for silicon photonic chips. You will shape the ASIC strategy, drive tapeouts across 130 nm and below, and mentor a small team of designers in a cutting-edge robotics and AI data-center environment.

The role emphasizes low-noise TIAs, mixed-signal design, and collaboration with photonics, FPGA, and digital teams, with a fast track to delivering silicon within 9–12 months.