Principal Microelectronics Engineer

Sanmina Corporation; Costa Mesa (CA); On-site; USD 90,000 - 150,000; Full time

Job summary

An established industry player is seeking a skilled leader in microelectronics packaging to drive innovative solutions for high-density memory products. This role involves leading a talented team in the design and development of advanced semiconductor packages for defense, aerospace, and commercial markets. You will be responsible for project management, technical guidance, and interfacing with both onshore and offshore partners. If you have a passion for cutting-edge technology and a proven track record in microelectronics, this is your chance to make a significant impact in a dynamic environment.

Qualifications

• 10-12 years of experience in microelectronics packaging.
• Solid understanding of semiconductor package design parameters.
• Experience leading cross-functional teams in complex projects.

Responsibilities

• Lead a team in developing DRAM and Flash products.
• Responsible for project scheduling and execution.
• Interface with assembly and test subcontractors.

Skills

Microelectronics Packaging

Project Management

Cross-Functional Team Leadership

Communication Skills

Wafer Level Packaging

Thermal Simulation

Signal Integrity Simulation

PCB Layout

Education

Bachelor's degree in Microelectronics Packaging

Bachelor's degree in Electrical Engineering

Bachelor's degree in Mechanical Engineering

Bachelor's degree in Physics

Bachelor's degree in Materials

Tools

SMT Processing Equipment

PCB Assembly

Job description

Job Purpose:

Candidate will lead the design and development of innovative microelectronics packaging solutions for high-density memory products targeted at the defense, aerospace, and commercial markets.

Nature of Duties/Responsibilities:

1. Lead a team of engineers and subcontractors in the development and qualification of DRAM and Flash products, including multichip modules (MCM), plastic ball grid array multichip packages (MCP), and System-In-Package (SiP) solutions.
2. Responsible for project scheduling, execution, status reporting, and providing technical guidance to the team.
3. Interface directly with onshore and offshore assembly and test subcontractors (OSAT) and OEM customers.
4. Some travel may be required.

Education and Experience:

• Minimum 10-12 years of related experience.
• Bachelor's degree in Microelectronics Packaging, EE, Mechanical Engineering, Physics, or Materials.
• Experience in the design of semiconductor packages such as plastic ball grid arrays, MultiChip Packages (MCPs), and System-in-Package (SiP).
• Solid understanding of semiconductor package design parameters and their influence on cost, thermal and electrical performance, reliability, and manufacturability.
• Experience leading cross-functional engineering teams in complex microelectronics packaging projects.
• Project management experience including scheduling, status reporting, and subcontractor management.
• Thorough understanding of microelectronics package design flow, including mechanical design, signal integrity simulation, thermal simulation, schematic capture, and PCB layout.
• Thorough understanding of high volume manufacturing processes for semiconductor ICs (backend packaging and test).
• Familiarity with silicon wafer post-process techniques such as wafer thinning, dicing, and RDL application.
• Understanding and experience in packaging qualification testing techniques and industry standard test methods.
• Experience interfacing directly with onshore and offshore microelectronics assembly and test subcontractors (OSAT).
• Experience with printed circuit board assembly, SMT processing equipment, and methods.
• Familiarity with integrated circuit functional test and burn-in techniques.
• Excellent verbal and written communication skills.

Packaging Skills:

• Wafer level packaging, wafer preparation (dicing, grinding, wafer expansion, die singulation).
• Die pick and place, die attach, die stack, MEMS die, flip chip, underfill, thermo-compression bonding, wirebond, molding (transfer mold), and other packaging techniques.
• Packages handled and developed include QFP, TQFP, SOP, TSOP, QFN, flip chip, Cu pillar flip chip, BGA, CSP, fan-out wafer-level packaging (FOWLP), 2.5DIC, 3DIC, through-mold vias, through-silicon vias.

Sanmina is an Equal Opportunity Employer - M/F/Veteran/Disability/Sexual Orientation/Gender Identity.

This is an ITAR facility. Must be US Citizen or lawful permanent resident.